[coreboot-gerrit] Patch set updated for coreboot: soc/intel/quark: Add minimal Quark SoC files
Leroy P Leahy (leroy.p.leahy@intel.com)
gerrit at coreboot.org
Sun Jan 31 04:00:40 CET 2016
Leroy P Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13439
-gerrit
commit 1de7c08a51efcb3681c0b921eb14cb7967ae1503
Author: Lee Leahy <lpleahyjr at gmail.com>
Date: Fri Jan 1 18:08:48 2016 -0800
soc/intel/quark: Add minimal Quark SoC files
Add the files for minimal Quark SoC support including HTML
documentation:
* Declare pei_data structure
* Declare sleep states and chipset_power_state structure
* Specify top of memory
* Empty FspUpdVpd.h file
TEST=None
Change-Id: If741f84904394780e1f29bd6ddbd81514c3e21c9
Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>
---
src/soc/intel/quark/Kconfig | 30 ++++
src/soc/intel/quark/Makefile.inc | 31 ++++
src/soc/intel/quark/include/soc/pei_wrapper.h | 60 ++++++++
src/soc/intel/quark/include/soc/pm.h | 33 +++++
src/soc/intel/quark/memmap.c | 22 +++
src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h | 171 ++++++++++++++++++++++
6 files changed, 347 insertions(+)
diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig
new file mode 100644
index 0000000..4bc3ebc
--- /dev/null
+++ b/src/soc/intel/quark/Kconfig
@@ -0,0 +1,30 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2015-2016 Intel Corp.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+config SOC_INTEL_QUARK
+ bool
+ help
+ Intel Quark support
+
+if SOC_INTEL_QUARK
+
+config CPU_SPECIFIC_OPTIONS
+ def_bool y
+ select ARCH_BOOTBLOCK_X86_32
+ select ARCH_RAMSTAGE_X86_32
+ select ARCH_ROMSTAGE_X86_32
+ select ARCH_VERSTAGE_X86_32
+
+endif # SOC_INTEL_QUARK
diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc
new file mode 100644
index 0000000..39d45fa
--- /dev/null
+++ b/src/soc/intel/quark/Makefile.inc
@@ -0,0 +1,31 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2015-2016 Intel Corporation.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+ifeq ($(CONFIG_SOC_INTEL_QUARK),y)
+
+subdirs-y += ../../../cpu/x86/tsc
+
+romstage-y += memmap.c
+
+ramstage-y += memmap.c
+
+CPPFLAGS_common += -I$(src)/soc/intel/quark/include
+
+# Currently used for microcode path.
+CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)
+
+ROMCCFLAGS := -mcpu=p4 -fno-simplify-phi -O2
+
+endif # CONFIG_SOC_INTEL_QUARK
diff --git a/src/soc/intel/quark/include/soc/pei_wrapper.h b/src/soc/intel/quark/include/soc/pei_wrapper.h
new file mode 100644
index 0000000..5328e76
--- /dev/null
+++ b/src/soc/intel/quark/include/soc/pei_wrapper.h
@@ -0,0 +1,60 @@
+/*
+ * UEFI PEI wrapper
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corporation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Google Inc. nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL GOOGLE INC BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _PEI_WRAPPER_H_
+#define _PEI_WRAPPER_H_
+
+#include <types.h>
+
+#define PEI_VERSION 22
+
+#define ABI_X86 __attribute__((regparm(0)))
+
+typedef void ABI_X86(*tx_byte_func)(unsigned char byte);
+
+struct pei_data {
+ uint32_t pei_version;
+
+ int boot_mode;
+
+ /* Data read from flash and passed into MRC */
+ const void *saved_data;
+ int saved_data_size;
+
+ /* Disable use of saved data (can be set by mainboard) */
+ int disable_saved_data;
+
+ /* Data from MRC that should be saved to flash */
+ void *data_to_save;
+ int data_to_save_size;
+} __attribute__((packed));
+
+typedef struct pei_data PEI_DATA;
+
+#endif /* _PEI_WRAPPER_H_ */
diff --git a/src/soc/intel/quark/include/soc/pm.h b/src/soc/intel/quark/include/soc/pm.h
new file mode 100644
index 0000000..f9ae027
--- /dev/null
+++ b/src/soc/intel/quark/include/soc/pm.h
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_PM_H_
+#define _SOC_PM_H_
+
+#include <stdint.h>
+
+/* Generic sleep state types */
+#define SLEEP_STATE_S0 0
+#define SLEEP_STATE_S3 3
+#define SLEEP_STATE_S5 5
+
+struct chipset_power_state {
+ uint32_t prev_sleep_state;
+} __attribute__ ((packed));
+
+struct chipset_power_state *fill_power_state(void);
+
+#endif
diff --git a/src/soc/intel/quark/memmap.c b/src/soc/intel/quark/memmap.c
new file mode 100644
index 0000000..8ac88bc
--- /dev/null
+++ b/src/soc/intel/quark/memmap.c
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cbmem.h>
+
+void *cbmem_top(void)
+{
+ return (void *)0x0afd0000;
+}
diff --git a/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h b/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h
new file mode 100644
index 0000000..2a11b20
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h
@@ -0,0 +1,171 @@
+/** @file
+
+Copyright (c) 2015-2016, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPUPDVPD_H__
+#define __FSPUPDVPD_H__
+
+#pragma pack(push, 1)
+
+#define MAX_CHANNELS_NUM 2
+#define MAX_DIMMS_NUM 2
+
+typedef struct {
+ UINT8 DimmId;
+ UINT32 SizeInMb;
+ UINT16 MfgId;
+ UINT8 ModulePartNum[20];/* Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes */
+} DIMM_INFO;
+
+typedef struct {
+ UINT8 ChannelId;
+ UINT8 DimmCount;
+ DIMM_INFO DimmInfo[MAX_DIMMS_NUM];
+} CHANNEL_INFO;
+
+typedef struct {
+ UINT8 Revision;
+ UINT16 DataWidth;
+ /** As defined in SMBIOS 3.0 spec
+ Section 7.18.2 and Table 75
+ **/
+ UINT8 MemoryType;
+ UINT16 MemoryFrequencyInMHz;
+ /** As defined in SMBIOS 3.0 spec
+ Section 7.17.3 and Table 72
+ **/
+ UINT8 ErrorCorrectionType;
+ UINT8 ChannelCount;
+ CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM];
+} FSP_SMBIOS_MEMORY_INFO;
+
+/** UPD data structure for FspMemoryInitApi
+**/
+typedef struct {
+
+/** Offset 0x0020
+**/
+ UINT64 Signature;
+
+/** Offset 0x0028 - Revision
+ Revision version of the MemoryInitUpd Region
+**/
+ UINT8 Revision;
+} MEMORY_INIT_UPD;
+
+/** UPD data structure for FspSiliconInitApi
+**/
+typedef struct {
+
+/** Offset 0x0200
+**/
+ UINT64 Signature;
+
+/** Offset 0x0208 - Revision
+ Revision version of the SiliconInitUpd Region
+**/
+ UINT8 Revision;
+} SILICON_INIT_UPD;
+
+#define FSP_UPD_SIGNATURE 0x244450554B525124 /* '$QRKUPD$' */
+#define FSP_MEMORY_INIT_UPD_SIGNATURE 0x244450554D454D24 /* '$MEMUPD$' */
+#define FSP_SILICON_INIT_UPD_SIGNATURE 0x244450555F495324 /* '$SI_UPD$' */
+
+/** UPD data structure. The UPD_DATA_REGION may contain some reserved or unused fields in the data structure. These fields are required to use the default values provided in the FSP binary. Intel always recommends copying the whole UPD_DATA_REGION from the flash to a local structure in the stack before overriding any field.
+**/
+typedef struct {
+
+/** Offset 0x0000
+**/
+ UINT64 Signature;
+
+/** Offset 0x0008 - This field is not an option and is a Revision of the UPD_DATA_REGION. It can be used by the boot loader to validate the UPD region. If the value in this field is changed for an FSP release, the boot loader should not assume the same layout for the UPD_DATA_REGION data structure. Instead it should use the new FspUpdVpd.h from the FSP release package.
+ Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build
+**/
+ UINT8 Revision;
+
+/** Offset 0x0009
+**/
+ UINT8 ReservedUpd0[7];
+
+/** Offset 0x0010 - MemoryInitUpdOffset
+ This field contains the offset of the MemoryInitUpd structure relative to UPD_DATA_REGION
+**/
+ UINT32 MemoryInitUpdOffset;
+
+/** Offset 0x0014 - SiliconInitUpdOffset
+ This field contains the offset of the SiliconInitUpd structure relative to UPD_DATA_REGION
+**/
+ UINT32 SiliconInitUpdOffset;
+
+/** Offset 0x0018
+**/
+ UINT64 ReservedUpd1;
+
+/** Offset 0x0020
+**/
+ MEMORY_INIT_UPD MemoryInitUpd;
+
+/** Offset 0x0200
+**/
+ SILICON_INIT_UPD SiliconInitUpd;
+
+/** Offset 0x03FA - RegionTerminator
+ This field is not an option and is a termination field at the end of the data structure. This field is will have a value 0x55AA indicating the end of UPD data.The boot loader should never override this field.
+**/
+ UINT16 RegionTerminator;
+} UPD_DATA_REGION;
+
+#define FSP_IMAGE_ID 0x305053462D4B5551 /* 'QUK-FSP0' */
+#define FSP_IMAGE_REV 0x00000000 /* 0.0 */
+
+/** VPD data structure
+**/
+typedef struct {
+
+/** Offset 0x0000
+**/
+ UINT64 PcdVpdRegionSign;
+
+/** Offset 0x0008 - PcdImageRevision
+ This field is not an option and is a revision ID for the FSP release. It can be used by the boot loader to validate the VPD/UPD region. If the value in this field is changed for an FSP release, the boot loader should not assume the same layout for the UPD_DATA_REGION/VPD_DATA_REGION data structure. Instead it should use the new FspUpdVpd.h from the FSP release package. This should match the ImageRevision in FSP_INFO_HEADER.
+**/
+ UINT32 PcdImageRevision;
+
+/** Offset 0x000C - PcdUpdRegionOffset
+ This field is not an option and contains the offset of the UPD data region within the FSP release image. The boot loader can use it to find the location of UPD_DATA_REGION.
+**/
+ UINT32 PcdUpdRegionOffset;
+} VPD_DATA_REGION;
+
+#pragma pack(pop)
+
+#endif
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