[coreboot-gerrit] Patch set updated for coreboot: soc/braswell: Fix issues found during static code analysis

[Hannah Williams (hannah.williams@intel.com)]

Hannah Williams (hannah.williams at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12738

-gerrit

commit 86881d04214c47c91437bed3f9e973395bd5f8fd
Author: Ravi Sarawadi <ravishankar.sarawadi at intel.com>
Date:   Wed Sep 9 14:12:16 2015 -0700

    soc/braswell: Fix issues found during static code analysis
    
    TEST=Build, boot to OS
    
    Original-Reviewed-on: https://chromium-review.googlesource.com/299483
    Original-Reviewed-by: Aaron Durbin <adurbin at google.com>
    
    Change-Id: I738003b8dfff6a5255085d39e378e18d6ad36bcf
    Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi at intel.com>
---
 src/mainboard/google/cyan/spd/spd.c        |  2 +-
 src/soc/intel/braswell/chip.c              | 10 +++++++++-
 src/soc/intel/braswell/pmutil.c            | 13 ++++---------
 src/soc/intel/braswell/romstage/romstage.c |  7 +++++++
 4 files changed, 21 insertions(+), 11 deletions(-)

diff --git a/src/mainboard/google/cyan/spd/spd.c b/src/mainboard/google/cyan/spd/spd.c
index 31f6911..5890204 100644
--- a/src/mainboard/google/cyan/spd/spd.c
+++ b/src/mainboard/google/cyan/spd/spd.c
@@ -135,7 +135,7 @@ void mainboard_fill_spd_data(struct pei_data *ps)
 static void set_dimm_info(uint32_t chips, uint8_t *spd, struct dimm_info *dimm)
 {
 	uint16_t clock_frequency;
-	uint32_t log2_chips;
+	uint32_t log2_chips = 0;
 
 	/* Parse the SPD data to determine the DIMM information */
 	dimm->ddr_type = MEMORY_TYPE_DDR3;
diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c
index 6cf3e8a..a0e6d21 100644
--- a/src/soc/intel/braswell/chip.c
+++ b/src/soc/intel/braswell/chip.c
@@ -84,7 +84,15 @@ static void enable_dev(device_t dev)
 void soc_silicon_init_params(SILICON_INIT_UPD *params)
 {
 	device_t dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));
-	struct soc_intel_braswell_config *config = dev->chip_info;
+	struct soc_intel_braswell_config *config;
+
+	if (!dev) {
+		printk(BIOS_ERR,
+			"Error! Device (%s) not found, soc_silicon_init_params!\n",dev_path(dev));
+		return;
+	}
+
+	config  = dev->chip_info;
 
 	/* Set the parameters for SiliconInit */
 	printk(BIOS_DEBUG, "Updating UPD values for SiliconInit\n");
diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c
index 4611510..018915c 100644
--- a/src/soc/intel/braswell/pmutil.c
+++ b/src/soc/intel/braswell/pmutil.c
@@ -68,11 +68,6 @@ static void print_num_status_bits(int num_bits, uint32_t status,
 	}
 }
 
-static void print_status_bits(uint32_t status, const char * const bit_names[])
-{
-	print_num_status_bits(32, status, bit_names);
-}
-
 static uint32_t print_smi_status(uint32_t smi_sts)
 {
 	static const char * const smi_sts_bits[] = {
@@ -99,7 +94,7 @@ static uint32_t print_smi_status(uint32_t smi_sts)
 		return 0;
 
 	printk(BIOS_DEBUG, "SMI_STS: ");
-	print_status_bits(smi_sts, smi_sts_bits);
+	print_num_status_bits(30, smi_sts, smi_sts_bits);
 	printk(BIOS_DEBUG, "\n");
 
 	return smi_sts;
@@ -175,7 +170,7 @@ static uint16_t print_pm1_status(uint16_t pm1_sts)
 		return 0;
 
 	printk(BIOS_SPEW, "PM1_STS: ");
-	print_status_bits(pm1_sts, pm1_sts_bits);
+	print_num_status_bits(16, pm1_sts, pm1_sts_bits);
 	printk(BIOS_SPEW, "\n");
 
 	return pm1_sts;
@@ -202,7 +197,7 @@ static uint32_t print_tco_status(uint32_t tco_sts)
 		return 0;
 
 	printk(BIOS_DEBUG, "TCO_STS: ");
-	print_status_bits(tco_sts, tco_sts_bits);
+	print_num_status_bits(18, tco_sts, tco_sts_bits);
 	printk(BIOS_DEBUG, "\n");
 
 	return tco_sts;
@@ -289,7 +284,7 @@ static uint32_t print_gpe_sts(uint32_t gpe_sts)
 		return gpe_sts;
 
 	printk(BIOS_DEBUG, "GPE0a_STS: ");
-	print_status_bits(gpe_sts, gpe_sts_bits);
+	print_num_status_bits(32, gpe_sts, gpe_sts_bits);
 	printk(BIOS_DEBUG, "\n");
 
 	return gpe_sts;
diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c
index 2581583..71402ac 100644
--- a/src/soc/intel/braswell/romstage/romstage.c
+++ b/src/soc/intel/braswell/romstage/romstage.c
@@ -200,6 +200,13 @@ void soc_memory_init_params(struct romstage_params *params,
 
 	/* Set the parameters for MemoryInit */
 	dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));
+
+	if (!dev) {
+		printk(BIOS_ERR,
+			"Error! Device (PCI:0:%02x.%01x) not found, soc_memory_init_params!\n", LPC_DEV, LPC_FUNC);
+		return;
+	}
+
 	config = dev->chip_info;
 	printk(BIOS_DEBUG, "Updating UPD values for MemoryInit\n");
 	upd->PcdMrcInitTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ?