[coreboot-gerrit] Patch set updated for coreboot: soc/braswell: Set max frequency to be turbo frequency

[Hannah Williams (hannah.williams@intel.com)]

Hannah Williams (hannah.williams at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12736

-gerrit

commit 01acb39c474511f5e53470de94c1cc2c59aeb8cb
Author: Hannah Williams <hannah.williams at intel.com>
Date:   Sun Aug 23 17:24:43 2015 -0700

    soc/braswell: Set max frequency to be turbo frequency
    
    In set_max_freq, instead of using ratio from IA_CORE_RATIOS, using
    ratio from MSR_IACORE_TURBO_RATIOS
    Also, punit_init needs to be called before enabling this frequency.
    
    Original-Reviewed-on: https://chromium-review.googlesource.com/295268
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Original-Tested-by: Hannah Williams <hannah.williams at intel.com>
    
    Change-Id: Iabdab9ec45f8eef0a105a5a05dbcdb997b6764b0
    Signed-off-by: Hannah Williams <hannah.williams at intel.com>
---
 src/soc/intel/braswell/ramstage.c | 1 +
 src/soc/intel/braswell/tsc_freq.c | 9 +++++++--
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c
index 1e085d7..155c8a2 100644
--- a/src/soc/intel/braswell/ramstage.c
+++ b/src/soc/intel/braswell/ramstage.c
@@ -196,6 +196,7 @@ void soc_init_pre_device(struct soc_intel_braswell_config *config)
 
 	/* Perform silicon specific init. */
 	intel_silicon_init();
+	set_max_freq();
 
 	set_board_id();
 	/* Get GPIO initial states from mainboard */
diff --git a/src/soc/intel/braswell/tsc_freq.c b/src/soc/intel/braswell/tsc_freq.c
index fff882e..f4f1a8b 100644
--- a/src/soc/intel/braswell/tsc_freq.c
+++ b/src/soc/intel/braswell/tsc_freq.c
@@ -72,18 +72,23 @@ void set_max_freq(void)
 	msr.lo |= (1 << 16);
 	wrmsr(MSR_IA32_MISC_ENABLES, msr);
 
+	/* Enable Burst Mode */
+	msr = rdmsr(MSR_IA32_MISC_ENABLES);
+	msr.hi = 0;
+	wrmsr(MSR_IA32_MISC_ENABLES, msr);
+
 	/*
 	 * Set guranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of
 	 * the PERF_CTL.
 	 */
-	msr = rdmsr(MSR_IACORE_RATIOS);
+	msr = rdmsr(MSR_IACORE_TURBO_RATIOS);
 	perf_ctl.lo = (msr.lo & 0x3f0000) >> 8;
 
 	/*
 	 * Set guranteed vid [21:16] from IACORE_VIDS to bits [7:0] of
 	 * the PERF_CTL.
 	 */
-	msr = rdmsr(MSR_IACORE_VIDS);
+	msr = rdmsr(MSR_IACORE_TURBO_VIDS);
 	perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16;
 	perf_ctl.hi = 0;