[coreboot-gerrit] Patch set updated for coreboot: Documentation: Add x86 documentation for required files
Leroy P Leahy (leroy.p.leahy@intel.com)
gerrit at coreboot.org
Thu Jan 28 02:54:21 CET 2016
Leroy P Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13438
-gerrit
commit f2b82301b5a0e1df40accee403db2055e1512609
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date: Thu Jan 7 11:24:24 2016 -0800
Documentation: Add x86 documentation for required files
Document the required files to perform a minimal coreboot/FSP build for
x86.
TEST=None
Change-Id: I65b2947114634fce982ce82fb7c577fd5f47ed10
Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>
---
Documentation/x86Development.html | 52 +++++++++++++++++
src/drivers/intel/fsp1_1/fsp1_1.html | 44 +++++++++++++++
src/mainboard/intel/board.html | 83 +++++++++++++++++++++++++++
src/soc/intel/soc.html | 105 +++++++++++++++++++++++++++++++++++
4 files changed, 284 insertions(+)
diff --git a/Documentation/x86Development.html b/Documentation/x86Development.html
new file mode 100644
index 0000000..e0369e4
--- /dev/null
+++ b/Documentation/x86Development.html
@@ -0,0 +1,52 @@
+<!DOCTYPE html>
+<html>
+ <head>
+ <title>Development</title>
+ </head>
+ <body>
+
+<h1>Coreboot/FSP Development Process for Intel x86</h1>
+<p>
+ The x86 development process for coreboot is broken into the following components:
+</p>
+<ul>
+ <li>Coreboot <a target="_blank" href="../src/soc/intel/soc.html">SoC</a> development</li>
+ <li>Coreboot <a target="_blank" href="../src/mainboard/intel/board.html">mainboard</a> development</li>
+ <li><a target="_blank" href="../src/drivers/intel/fsp1_1/fsp1_1.html">FSP 1.1</a> integration</li>
+</ul>
+<p>
+ The combined steps below describe how to bring up coreboot for a
+ system-on-a-chip (SoC) and a development board:
+</p>
+<table>
+ <tr bgcolor="#ffffc0">
+ <td>The initial coreboot steps are single threaded!
+ The initial minimal FSP development is also single threaded.
+ Progress can speed up by adding more developers after the minimal coreboot/FSP
+ implementation reaches the payload.
+ </td>
+ </tr>
+</table>
+<ol>
+ <li>Get and build the necessary tools:
+ <ol type="A">
+ <li>sudo apt-get install m4 bison flex ncurses-dev</li>
+ <li>make crossgcc</li>
+ </ol>
+ </li>
+ <li>Get something to build:
+ <ol type="A">
+ <li><a target="_blank" href="../src/drivers/intel/fsp1_1/fsp1_1.html#RequiredFiles">FSP 1.1</a> required files</li>
+ <li><a target="_blank" href="../src/soc/intel/soc.html#RequiredFiles">SoC</a> required files</li>
+ <li><a target="_blank" href="../src/mainboard/intel/board.html#RequiredFiles">Board</a> required files</li>
+ </ol>
+ </li>
+ <li>Get result to start <a target="_blank" href="../src/soc/intel/soc.html#Descriptor">booting</a></li>
+ <li><a target="_blank" href="../src/soc/intel/soc.html#EarlyDebug">Early Debug</a></li>
+</ol>
+
+
+<hr>
+<p>Modified: 27 January 2016</p>
+ </body>
+</html>
\ No newline at end of file
diff --git a/src/drivers/intel/fsp1_1/fsp1_1.html b/src/drivers/intel/fsp1_1/fsp1_1.html
new file mode 100644
index 0000000..dcfd588
--- /dev/null
+++ b/src/drivers/intel/fsp1_1/fsp1_1.html
@@ -0,0 +1,44 @@
+<!DOCTYPE html>
+<html>
+ <head>
+ <title>FSP 1.1</title>
+ </head>
+ <body>
+
+<h1>x86 FSP 1.1 Development</h1>
+<p>
+ Firmware Support Package (FSP) development requires System-on-a-Chip (SoC)
+ and board support. The combined steps are listed
+ <a target="_blank" href="../../../../Documentation/x86Development.html">here</a>.
+ The development steps for FSP are listed below:
+</p>
+<ol>
+ <li><a href="#RequiredFiles">Required Files</a></li>
+</ol>
+
+
+<hr>
+<h1><a name="RequiredFiles">Required Files</a></h1>
+<h2><a name="CorebootRequiredFiles">Coreboot Required Files</a></h2>
+<ol>
+ <li>Create the directories:
+ <ul>
+ <li>src/vendorcode/intel/fsp/fsp1_1/<Chip Family></li>
+ <li>3rdparty/blobs/mainboard/<Board Vendor>/<Board Name></li>
+ </ul>
+ </li>
+ <li>
+ The following files need to be copied from the FSP build or release into the
+ directories above:
+ <ul>
+ <li>FspUpdVpd.h: src/vendorcode/intel/fsp/fsp1_1/<Chip Family>/FspUpdVpd.h</li>
+ <li>FSP.bin: 3rdparty/blobs/mainboard/<Board Vendor>/<Board Name>/fsp.bin</li>
+ </ul>
+ </li>
+</ol>
+
+
+<hr>
+<p>Modified: 27 January 2016</p>
+ </body>
+</html>
\ No newline at end of file
diff --git a/src/mainboard/intel/board.html b/src/mainboard/intel/board.html
new file mode 100644
index 0000000..a7b5b32
--- /dev/null
+++ b/src/mainboard/intel/board.html
@@ -0,0 +1,83 @@
+<!DOCTYPE html>
+<html>
+ <head>
+ <title>Board</title>
+ </head>
+ <body>
+
+<h1>x86 Board Development</h1>
+<p>
+ Board development requires System-on-a-Chip (SoC) support.
+ The combined steps are listed
+ <a target="_blank" href="../../../Documentation/x86Development.html">here</a>.
+ The development steps for the board are listed below:
+</p>
+<ol>
+ <li><a href="#RequiredFiles">Required Files</a></li>
+</ol>
+
+
+<hr>
+<h1><a name="RequiredFiles">Required Files</a></h1>
+<p>
+ Create the board directory as src/mainboard/<Vendor>/<Board>.
+</p>
+
+<p>
+ The following files are required to build a new board:
+</p>
+<ol>
+ <li>Kconfig.name - Defines the Kconfig value for the board</li>
+ <li>Kconfig
+ <ol type="A">
+ <li>Selects the SoC for the board and specifies the SPI flash size
+ <ol type="I">
+ <li>BOARD_ROMSIZE_KB_<Size></li>
+ <li>SOC_<Vendor>_<Chip Family></li>
+ </ol>
+ </li>
+ <li>Declare the Kconfig values for:
+ <ol type="I">
+ <li>MAINBOARD_DIR</li>
+ <li>MAINBOARD_PART_NUMBER</li>
+ <li>MAINBOARD_VENDOR</li>
+ </ol>
+ </li>
+ </ol>
+ </li>
+ <li>devicetree.cb - Enable root bridge and serial port
+ <ol type="A">
+ <li>The first line must be "chip soc/Intel/<soc family>";
+ this path is used by the generated static.c to include the chip.h
+ header file
+ </li>
+ </ol>
+ </li>
+ <li>romstage.c
+ <ol type="A">
+ <li>Add routine mainboard_romstage_entry which calls romstage_common</li>
+ </ol>
+ </li>
+ <li>Configure coreboot build:
+ <ol type="A">
+ <li>Set LOCALVERSION</li>
+ <li>FLASHMAP_OFFSET = 0x00700000</li>
+ <li>Select vendor for the board</li>
+ <li>Select the board</li>
+ <LI>CBFS_SIZE = 0x00100000</li>
+ <li>Set the CPU_MICROCODE_CBFS_LEN</li>
+ <li>Set the CPU_MICROCODE_CBFS_LOC</li>
+ <li>Set the FSP_IMAGE_ID_STRING</li>
+ <li>Set the FSP_LOC</li>
+ <li>Disable GOP_SUPPORT</li>
+ <li>No payload</li>
+ <li>Choose the default value for all other options</li>
+ </ol>
+ </li>
+</ol>
+
+
+<hr>
+<p>Modified: 27 January 2016</p>
+ </body>
+</html>
\ No newline at end of file
diff --git a/src/soc/intel/soc.html b/src/soc/intel/soc.html
new file mode 100644
index 0000000..0778c4d
--- /dev/null
+++ b/src/soc/intel/soc.html
@@ -0,0 +1,105 @@
+<!DOCTYPE html>
+<html>
+ <head>
+ <title>SoC</title>
+ </head>
+ <body>
+
+<h1>x86 System on a Chip (SoC) Development</h1>
+<p>
+ SoC development is best done in parallel with development for a specific
+ board. The combined steps are listed
+ <a target="_blank" href="../../../Documentation/x86Development.html">here</a>.
+ The development steps for the SoC are listed below:
+</p>
+<ol>
+ <li><a target="_blank" href="../../drivers/intel/fsp1_1/fsp1_1.html#RequiredFiles">FSP 1.1</a> required files</li>
+ <li>SoC <a href="#RequiredFiles">Required Files</a></li>
+ <li><a href="#Descriptor">Start Booting</a></li>
+ <li><a href="#EarlyDebug">Early Debug</a></li>
+</ol>
+
+
+<hr>
+<h1><a name="RequiredFiles">Required Files</a></h1>
+<p>
+ Create the directory as src/soc/<Vendor>/<Chip Family>.
+</p>
+
+<p>
+ The following files are required to build a new SoC:
+</p>
+<ul>
+ <li>Include files
+ <ul>
+ <li>include/soc/pei_data.h</li>
+ <li>include/soc/pm.h</li>
+ </ul>
+ </li>
+ <li>Kconfig - Defines the Kconfig value for the SoC and selects the tool
+ chains for the various stages:
+ <ul>
+ <li>select ARCH_BOOTBLOCK_<Tool Chain></li>
+ <li>select ARCH_RAMSTAGE_<Tool Chain></li>
+ <li>select ARCH_ROMSTAGE_<Tool Chain></li>
+ <li>select ARCH_VERSTAGE_<Tool Chain></li>
+ </ul>
+ </li>
+ <li>Makefile.inc - Specify the include paths</li>
+ <li>memmap.c - Top of usable RAM</li>
+</ul>
+
+
+<hr>
+<h1><a name="Descriptor">Start Booting</a></h1>
+<p>
+ Some SoC parts require additional firmware components in the flash.
+ This section describes how to add those pieces.
+</p>
+
+<h2>Intel Firmware Descriptor</h2>
+<p>
+ The Intel Firmware Descriptor (IFD) is located at the base of the flash part.
+ The following command overwrites the base of the flash image with the Intel
+ Firmware Descriptor:
+</p>
+<pre><code>dd if=descriptor.bin of=build/coreboot.rom conv=notrunc >/dev/null 2>&1</code></pre>
+
+
+<h2><a name="MEB">Management Engine Binary</a></h2>
+<p>
+ Some SoC parts contain and require that the Management Engine (ME) be running
+ before it is possible to bring the x86 processor out of reset. A binary file
+ containing the management engine code must be added to the firmware using the
+ ifdtool. The following commands add this binary blob:
+</p>
+<pre><code>util/ifdtool/ifdtool -i ME:me.bin build/coreboot.rom
+mv build/coreboot.rom.new build/coreboot.rom
+</code></pre>
+
+
+<h2><a name="EarlyDebug">Early Debug</a></h2>
+<p>
+ Early debugging between the reset vector and the time the serial port is enabled
+ is most easily done by writing values to port 0x80.
+</p>
+
+
+<h2>Success</h2>
+<p>
+ When the reset vector is successfully invoked, port 0x80 will output the following value:
+</p>
+<ul>
+ <li>0x01: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l45">POST_RESET_VECTOR_CORRECT</a>
+ - Bootblock successfully executed the
+ <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/reset16.inc;hb=HEAD#l4">reset vector</a>
+ and entered the 16-bit code at
+ <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/entry16.inc;hb=HEAD#l35">_start</a>
+ </li>
+</ul>
+
+
+<hr>
+<p>Modified: 27 January 2016</p>
+ </body>
+</html>
\ No newline at end of file
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