[coreboot-gerrit] Patch set updated for coreboot: intel/strago: Update DPTF parameters to higher temperature.

[Hannah Williams (hannah.williams@intel.com)]

Hannah Williams (hannah.williams at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13484

-gerrit

commit 782d816b319e5f015ea86b8f17d2b3a1cb4d62f7
Author: Divagar Mohandass <divagar.mohandass at intel.com>
Date:   Tue Sep 29 15:01:58 2015 +0530

    intel/strago: Update DPTF parameters to higher temperature.
    
    Fish bowl HTML5 graphics benchmark with 250 fish
    is not reaching 60 FPS. This change will update
    the DPTF parameters to accommodate this test.
    
    TEST=Run fish bowl benchmark with 250 fish
    and check for 60 FPS.
    
    Change-Id: I6b6827199cb0f5ab44c354abc477ea73e4de9ec5
    Original-Signed-off-by: Divagar Mohandass <divagar.mohandass at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/302208
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/intel/strago/acpi/dptf.asl | 27 ++++++++-------------------
 src/mainboard/intel/strago/onboard.h     |  3 +++
 2 files changed, 11 insertions(+), 19 deletions(-)

diff --git a/src/mainboard/intel/strago/acpi/dptf.asl b/src/mainboard/intel/strago/acpi/dptf.asl
index b875b93..2a95703 100755
--- a/src/mainboard/intel/strago/acpi/dptf.asl
+++ b/src/mainboard/intel/strago/acpi/dptf.asl
@@ -16,19 +16,19 @@
 
 #define DPTF_TSR0_SENSOR_ID	0
 #define DPTF_TSR0_SENSOR_NAME	"TMP432_Internal"
-#define DPTF_TSR0_PASSIVE	48
-#define DPTF_TSR0_CRITICAL	70
+#define DPTF_TSR0_PASSIVE	49
+#define DPTF_TSR0_CRITICAL	75
 
 
 #define DPTF_TSR1_SENSOR_ID	1
 #define DPTF_TSR1_SENSOR_NAME	"TMP432_Power_top"
-#define DPTF_TSR1_PASSIVE	60
-#define DPTF_TSR1_CRITICAL	70
+#define DPTF_TSR1_PASSIVE	65
+#define DPTF_TSR1_CRITICAL	85
 
 #define DPTF_TSR2_SENSOR_ID	2
 #define DPTF_TSR2_SENSOR_NAME	"TMP432_CPU_bottom"
-#define DPTF_TSR2_PASSIVE	55
-#define DPTF_TSR2_CRITICAL	70
+#define DPTF_TSR2_PASSIVE	49
+#define DPTF_TSR2_CRITICAL	75
 
 
 #define DPTF_ENABLE_CHARGER
@@ -50,18 +50,7 @@ Name (DTRT, Package () {
 	Package () { \_SB.PCI0.B0DB, \_SB.PCI0.B0DB, 100, 50, 0, 0, 0, 0 },
 
 	/* CPU Effect on Temp Sensor 0 */
-	Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
-
-#ifdef DPTF_ENABLE_CHARGER
-	/* Charger Effect on Temp Sensor 1 */
-	Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 },
-#endif
-
-	/* CPU Effect on Temp Sensor 1 */
-	Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
-
-	/* CPU Effect on Temp Sensor 2 */
-	Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
+	Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR0, 100, 100, 0, 0, 0, 0 },
 })
 
 Name (MPPC, Package ()
@@ -69,7 +58,7 @@ Name (MPPC, Package ()
 	0x2,		/* Revision */
 	Package () {	/* Power Limit 1 */
 		0,	/* PowerLimitIndex, 0 for Power Limit 1 */
-		1600,	/* PowerLimitMinimum */
+		2000,	/* PowerLimitMinimum */
 		6200,	/* PowerLimitMaximum */
 		1000,	/* TimeWindowMinimum */
 		1000,	/* TimeWindowMaximum */
diff --git a/src/mainboard/intel/strago/onboard.h b/src/mainboard/intel/strago/onboard.h
index 89c9b69..d93608b 100755
--- a/src/mainboard/intel/strago/onboard.h
+++ b/src/mainboard/intel/strago/onboard.h
@@ -74,4 +74,7 @@
 
 #define BCRD2_PMIC_I2C_BUS		0x01
 
+#define DPTF_CPU_PASSIVE	88
+#define DPTF_CPU_CRITICAL	90
+
 #endif