[coreboot-gerrit] Patch set updated for coreboot: soc/apollolake: Rewrite assembly files in ATT syntax
Alexandru Gagniuc (mr.nuke.me@gmail.com)
gerrit at coreboot.org
Wed Jan 27 22:58:22 CET 2016
Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13492
-gerrit
commit 459032c984204fbd7ade71483e1fb4b411d7cc65
Author: Alexandru Gagniuc <alexandrux.gagniuc at intel.com>
Date: Wed Jan 27 10:06:18 2016 -0800
soc/apollolake: Rewrite assembly files in ATT syntax
When we stared development internally, both intel and att syntaxes
were accepted. Since our hardware debuggers only work with intel
syntax, it proved much more productive with regards to development
and debugging time to use intel syntax in the code.
Recently, the coreboot leadership has updated the guidelines to
converge on att syntax. Rewrite all appololake assembly files to be
compliant with this new guideline.
Change-Id: Ief78cba4a771fc6549ee204f5df81bc93245a4a1
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc at intel.com>
---
src/soc/intel/apollolake/bootblock/cache_as_ram.S | 85 ++++++++++------------
.../apollolake/bootblock/early_chipset_config.S | 44 +++++------
src/soc/intel/apollolake/romstage/entry.inc | 5 +-
3 files changed, 61 insertions(+), 73 deletions(-)
diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram.S b/src/soc/intel/apollolake/bootblock/cache_as_ram.S
index 6ecfa86..1713877 100644
--- a/src/soc/intel/apollolake/bootblock/cache_as_ram.S
+++ b/src/soc/intel/apollolake/bootblock/cache_as_ram.S
@@ -21,101 +21,96 @@
#define EVICT_CTL_MSR 0x2e0
-.intel_syntax noprefix
-
-#undef post_code
-#define post_code(value) \
- mov al, value; \
- outb CONFIG_POST_IO_PORT, al
.global cache_as_ram
cache_as_ram:
post_code(0x21)
/* Clear/disable fixed MTRRs */
- mov ebx, offset fixed_mtrr_list_size
- xor eax, eax
- xor edx, edx
+ mov $fixed_mtrr_list_size, %ebx
+ xor %eax, %eax
+ xor %edx, %edx
clear_fixed_mtrr:
- add ebx, -2
- movzxw ecx, word ptr [fixed_mtrr_list + ebx]
+ add $-2, %ebx
+ movzwl fixed_mtrr_list(%ebx), %ecx
wrmsr
jnz clear_fixed_mtrr
post_code(0x22)
/* Figure put how many MTRRs we have, and clear them out */
- mov ecx, MTRR_CAP_MSR
+ mov $MTRR_CAP_MSR, %ecx
rdmsr
- movzxb ebx, al /* Number of variable MTRRs */
- mov ecx, MTRR_PHYS_BASE(0)
- xor eax, eax
- xor edx, edx
+ movzb %al, %ebx /* Number of variable MTRRs */
+ mov $MTRR_PHYS_BASE(0), %ecx
+ xor %eax, %eax
+ xor %edx, %edx
+
clear_var_mtrr:
wrmsr
- inc ecx
+ inc %ecx
wrmsr
- inc ecx
- dec ebx
+ inc %ecx
+ dec %ebx
jnz clear_var_mtrr
post_code(0x23)
/* Configure default memory type to uncacheable (UC) */
- mov ecx, MTRR_DEF_TYPE_MSR
+ mov $MTRR_DEF_TYPE_MSR, %ecx
rdmsr
- and eax, ~0xcff
+ and $~0xcff, %eax
wrmsr
post_code(0x24)
/* Configure CAR region as write-back (WB) */
- mov ecx, MTRR_PHYS_BASE(0)
- mov eax, CONFIG_DCACHE_RAM_BASE /* base */
- or eax, MTRR_TYPE_WRBACK
- xor edx, edx
+ mov $MTRR_PHYS_BASE(0), %ecx
+ mov $CONFIG_DCACHE_RAM_BASE, %eax
+ or $MTRR_TYPE_WRBACK, %eax
+ xor %edx,%edx
wrmsr
/* Configure the MTRR mask for the size region */
- mov ecx, MTRR_PHYS_MASK(0)
- mov eax, ~(CONFIG_DCACHE_RAM_SIZE - 1) /* size mask */
- or eax, MTRR_PHYS_MASK_VALID
+ mov $MTRR_PHYS_MASK(0), %ecx
+ mov $~(CONFIG_DCACHE_RAM_SIZE - 1), %eax /* size mask */
+ or $0x800, %eax
wrmsr
post_code(0x25)
/* Enable variable MTRRs */
- mov ecx, MTRR_DEF_TYPE_MSR
+ mov $MTRR_DEF_TYPE_MSR, %ecx
rdmsr
- or eax, MTRR_DEF_TYPE_EN
+ or $MTRR_DEF_TYPE_EN, %eax
wrmsr
/* Cache tricks */
- mov eax, cr0
- and eax, ~(CR0_CACHE_DISABLE | CR0_NO_WRITE)
+ mov %cr0, %eax
+ and $~(CR0_CACHE_DISABLE | CR0_NO_WRITE), %eax
invd
- mov cr0, eax
+ mov %eax, %cr0
/* Disable cache eviction (setup stage) */
- mov ecx, EVICT_CTL_MSR
+ mov $EVICT_CTL_MSR, %ecx
rdmsr
- or eax, 1
+ or $0x1, %eax
wrmsr
post_code(0x26)
/* Clear the cache memory region. This will also fill up the cache */
- mov edi, CONFIG_DCACHE_RAM_BASE
- mov ecx, CONFIG_DCACHE_RAM_SIZE >> 2
- xor eax, eax
- rep stos dword ptr es:[edi], eax
+ mov $CONFIG_DCACHE_RAM_BASE, %edi
+ mov $(CONFIG_DCACHE_RAM_SIZE >> 2), %ecx
+ xor %eax, %eax
+ rep stos %eax, %es:(%edi)
post_code(0x27)
/* Disable cache eviction (run stage) */
- mov ecx, EVICT_CTL_MSR
+ mov $EVICT_CTL_MSR, %ecx
rdmsr
- or eax, 2
+ or $0x2, %eax
wrmsr
post_code(0x28)
@@ -123,13 +118,13 @@ clear_var_mtrr:
car_init_done:
/* Setup bootblock stack */
- mov esp, CONFIG_DCACHE_RAM_BASE
- add esp, CONFIG_DCACHE_RAM_BOOTBLOCK_STACK_SIZE
+ mov $CONFIG_DCACHE_RAM_BASE, %esp
+ add $CONFIG_DCACHE_RAM_BOOTBLOCK_STACK_SIZE, %esp
/* Make sure CAR region is executable */
- mov ecx, 0x120
+ mov $0x120, %ecx
rdmsr
- or ah, 0x1
+ or $0x1, %ah
wrmsr
before_carstage:
diff --git a/src/soc/intel/apollolake/bootblock/early_chipset_config.S b/src/soc/intel/apollolake/bootblock/early_chipset_config.S
index a673a28..4f35211 100644
--- a/src/soc/intel/apollolake/bootblock/early_chipset_config.S
+++ b/src/soc/intel/apollolake/bootblock/early_chipset_config.S
@@ -10,6 +10,7 @@
* (at your option) any later version.
*/
+#include <cpu/x86/post_code.h>
#include <soc/gpio_defs.h>
/* Definitions used only here, for getting the MMIO base of LPC pad registers */
@@ -17,47 +18,40 @@
#define PAD_MMIO_ADDR(pad) (CONFIG_IOSF_BASE_ADDRESS + XLATE_LPC(pad))
-.intel_syntax noprefix
-.extern cache_as_ram
-
-#define post_code(value) \
- mov al, value; \
- outb CONFIG_POST_IO_PORT, al
-
.global bootblock_pre_c_entry
bootblock_pre_c_entry:
/*
* eax: BIST value
*/
- movd mm2, eax
+ movd %eax, %mm2
post_code(0x20)
enable_pciex_bar:
- mov eax, 0x80000060 /* ROOT PCI device reg60 PCIEX_BAR_*/
- mov dx, 0xcf8
- out dx, eax
- mov eax, (CONFIG_MMCONF_BASE_ADDRESS | 1)
- mov dx, 0xcfc
- out dx, eax
+ mov $0x80000060, %eax /* ROOT PCI device reg60 PCIEX_BAR_*/
+ mov $0xcf8, %dx
+ out %eax, %dx
+ mov $(CONFIG_MMCONF_BASE_ADDRESS | 1), %eax
+ mov $0xcfc, %dx
+ out %eax, %dx
enable_iosf_bar:
- mov ebp, 0xe0068000 /* IOSF PCI device */
- mov dword ptr [ebp + 0x10], CONFIG_IOSF_BASE_ADDRESS /* BAR 0 */
- mov word ptr [ebp + 0x04], 0x06 /* PCI command */
+ mov $0xe0068000, %ebp /* IOSF PCI device */
+ movl $CONFIG_IOSF_BASE_ADDRESS, 0x10(%ebp) /* BAR 0 */
+ movl $0x06, 0x04(%ebp) /* PCI command */
/* We need LPC for port80, but it won't work if the pads are not configured */
configure_lpc_pads:
- mov ecx, offset num_lpc_pads /* Number of pads to configure */
- lea esi, lpc_pad_params
+ mov $num_lpc_pads, %ecx /* Number of pads to configure */
+ lea lpc_pad_params, %esi
init_lpc_pad:
- mov edi, [esi + 0x00] /* MMIO addr of pad config registers */
- mov eax, [esi + 0x04] /* Pad CONF0 value */
- mov edx, [esi + 0x08] /* Pad CONF1 value */
- mov [edi + 0x00], eax /* Write CONF0 to config register */
- mov [edi + 0x04], edx /* Write CONF1 to config register */
- add esi, 0x0c
+ mov 0x00(%esi), %edi /* MMIO addr of pad config registers */
+ mov 0x04(%esi), %eax /* Pad CONF0 value */
+ mov 0x08(%esi), %edx /* Pad CONF1 value */
+ mov %eax, 0x00(%edi) /* Write CONF0 to config register */
+ mov %edx, 0x04(%edi) /* Write CONF1 to config register */
+ add $0x0c, %esi
loop init_lpc_pad
jmp cache_as_ram
diff --git a/src/soc/intel/apollolake/romstage/entry.inc b/src/soc/intel/apollolake/romstage/entry.inc
index 2c6dfd6..2e018ae 100644
--- a/src/soc/intel/apollolake/romstage/entry.inc
+++ b/src/soc/intel/apollolake/romstage/entry.inc
@@ -10,13 +10,12 @@
* (at your option) any later version.
*/
-.intel_syntax noprefix
apollolake_entry:
/*
* TODO: Make sure the stack does not clash with .car.data.
*/
- mov esp, (CONFIG_DCACHE_RAM_BASE + 0x4000)
+ mov $(CONFIG_DCACHE_RAM_BASE + 0x4000), %esp
call romstage_entry
@@ -25,7 +24,7 @@ apollolake_entry:
* to use as stack. The old stack is empty at this point, so we don't
* have to relocate anything.
*/
- mov esp, eax
+ mov %eax, %esp
/*
* TODO: set up temporary cache for RAM
More information about the coreboot-gerrit
mailing list