[coreboot-gerrit] Patch set updated for coreboot: mainboard/asus/kgpe-d16: Use W83667HG-A SuperIO instead of NCT5572D

[Timothy Pearson (tpearson@raptorengineeringinc.com)]

Timothy Pearson (tpearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13157

-gerrit

commit f3ef64c6fef83e15243f52bfcb13049f2ccb0287
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date:   Tue Nov 24 14:11:57 2015 -0600

    mainboard/asus/kgpe-d16: Use W83667HG-A SuperIO instead of NCT5572D
    
    Change-Id: If67999098fbe2831eeb30cb8b362c558db5d2688
    Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
---
 src/mainboard/asus/kgpe-d16/Kconfig       |  2 +-
 src/mainboard/asus/kgpe-d16/devicetree.cb | 16 +++++++++-------
 src/mainboard/asus/kgpe-d16/romstage.c    |  8 ++++----
 3 files changed, 14 insertions(+), 12 deletions(-)

diff --git a/src/mainboard/asus/kgpe-d16/Kconfig b/src/mainboard/asus/kgpe-d16/Kconfig
index f394ca9..23c91f0 100644
--- a/src/mainboard/asus/kgpe-d16/Kconfig
+++ b/src/mainboard/asus/kgpe-d16/Kconfig
@@ -12,7 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select SOUTHBRIDGE_AMD_SB700
 	select SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA
 	select SOUTHBRIDGE_AMD_SUBTYPE_SP5100
-	select SUPERIO_NUVOTON_NCT5572D
+	select SUPERIO_WINBOND_W83667HG_A
 	select PARALLEL_CPU_INIT
 	select HAVE_ROMSTAGE_CONSOLE_SPINLOCK
 	select HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK
diff --git a/src/mainboard/asus/kgpe-d16/devicetree.cb b/src/mainboard/asus/kgpe-d16/devicetree.cb
index 96372f9..8d64ac7 100644
--- a/src/mainboard/asus/kgpe-d16/devicetree.cb
+++ b/src/mainboard/asus/kgpe-d16/devicetree.cb
@@ -177,24 +177,27 @@ chip northbridge/amd/amdfam10/root_complex	# Root complex
 					device pci 14.1 on end			# IDE 0x439c
 					device pci 14.2 on end			# HDA 0x4383 (ASUS MIO add-on card)
 					device pci 14.3 on			# LPC 0x439d (SMBUS primary controller)
-						chip superio/nuvoton/nct5572d	# Super I/O
+						chip superio/winbond/w83667hg-a	# Super I/O
 							device pnp 2e.0 off end	# FDC; Not available on the KGPE-D16
 							device pnp 2e.1 off end	# LPT1; Not available on the KGPE-D16
 							device pnp 2e.2 on #  Com1
 								io 0x60 = 0x3f8
 								irq 0x70 = 4
 							end
-							device pnp 2e.3 off end	# IR: Not available on the KGPE-D16
+							device pnp 2e.3 on #  Com2
+								io 0x60 = 0x2f8
+								irq 0x70 = 3
+							end
 							device pnp 2e.5 on	# PS/2 keyboard & mouse
 								io 0x60 = 0x60
 								io 0x62 = 0x64
 								irq 0x70 = 1
 								irq 0x72 = 12
 							end
-							device pnp 2e.6 off end	# CIR: Not available on the KGPE-D16
-							device pnp 2e.7 off end	# GIPO689
+							device pnp 2e.6 off end	# SPI: Not available on the KGPE-D16
+							device pnp 2e.7 off end	# GIPO6789
 							device pnp 2e.8 off end	# WDT
-							device pnp 2e.9 off end	# GPIO235
+							device pnp 2e.9 off end	# GPIO2345
 							device pnp 2e.a on end	# ACPI
 							device pnp 2e.b on	# HW Monitor
 								io 0x60 = 0x290
@@ -202,8 +205,7 @@ chip northbridge/amd/amdfam10/root_complex	# Root complex
 								irq 0x70 = 5
 							end
 							device pnp 2e.c off end	# PECI
-							device pnp 2e.d off end	# SUSLED
-							device pnp 2e.e off end	# CIRWKUP
+							device pnp 2e.d off end	# VID_BUSSEL
 							device pnp 2e.f off end	# GPIO_PP_OD
 						end
 					end
diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c
index 13af96f..89183cc 100644
--- a/src/mainboard/asus/kgpe-d16/romstage.c
+++ b/src/mainboard/asus/kgpe-d16/romstage.c
@@ -35,8 +35,8 @@
 #include <delay.h>
 #include <cpu/x86/lapic.h>
 #include "northbridge/amd/amdfam10/reset_test.c"
-#include <superio/nuvoton/common/nuvoton.h>
-#include <superio/nuvoton/nct5572d/nct5572d.h>
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83667hg-a/w83667hg-a.h>
 #include <cpu/x86/bist.h>
 #include <smp/spinlock.h>
 // #include "northbridge/amd/amdk8/incoherent_ht.c"
@@ -46,7 +46,7 @@
 #include "northbridge/amd/amdfam10/debug.c"
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
 
-#define SERIAL_DEV PNP_DEV(0x2e, NCT5572D_SP1)
+#define SERIAL_DEV PNP_DEV(0x2e, W83667HG_A_SP1)
 
 static void activate_spd_rom(const struct mem_controller *ctrl);
 
@@ -393,7 +393,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		sb7xx_51xx_pci_port80();
 
 		/* Initialize early serial */
-		nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+		winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 		console_init();
 
 		/* Disable LPC legacy DMA support to prevent lockup */