[coreboot-gerrit] Patch set updated for coreboot: nb/intel/x4x: Move to early cbmem
Damien Zammit (damien@zamaudio.com)
gerrit at coreboot.org
Wed Jan 27 03:50:17 CET 2016
Damien Zammit (damien at zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13131
-gerrit
commit d551479cbc13a0121bfb364a49479a40bcf1eceb
Author: Damien Zammit <damien at zamaudio.com>
Date: Fri Jan 22 22:12:30 2016 +1100
nb/intel/x4x: Move to early cbmem
Previously with errors in the ram init, early cbmem was disabled.
Now that the ram is working correctly, set as early cbmem platform
and update all (1) boards to use it.
Tested on GA-G41M-ES2L
Change-Id: I5925c28821537f0e326b4f5a2ac39778e4724a3c
Signed-off-by: Damien Zammit <damien at zamaudio.com>
---
src/mainboard/gigabyte/ga-g41m-es2l/romstage.c | 1 +
src/northbridge/intel/x4x/Kconfig | 2 +-
src/northbridge/intel/x4x/northbridge.c | 3 ---
src/northbridge/intel/x4x/ram_calc.c | 7 +++++++
4 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
index 6bae128..ca8ca5c 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
@@ -159,5 +159,6 @@ void main(unsigned long bist)
printk(BIOS_DEBUG, "Initializing memory\n");
sdram_initialize(0, spd_addrmap);
quick_ram_check();
+ cbmem_initialize_empty();
printk(BIOS_DEBUG, "Memory initialized\n");
}
diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig
index c330fd5..f643bb2 100644
--- a/src/northbridge/intel/x4x/Kconfig
+++ b/src/northbridge/intel/x4x/Kconfig
@@ -26,7 +26,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
select MMCONF_SUPPORT_DEFAULT
select VGA
select INTEL_GMA_ACPI
- select LATE_CBMEM_INIT
+ select EARLY_CBMEM_INIT
config BOOTBLOCK_NORTHBRIDGE_INIT
string
diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c
index b23f8e6..827d2ba 100644
--- a/src/northbridge/intel/x4x/northbridge.c
+++ b/src/northbridge/intel/x4x/northbridge.c
@@ -28,7 +28,6 @@
#include <arch/acpi.h>
#include <northbridge/intel/x4x/chip.h>
#include <northbridge/intel/x4x/x4x.h>
-#include <cbmem.h>
static void mch_domain_read_resources(device_t dev)
{
@@ -111,8 +110,6 @@ static void mch_domain_read_resources(device_t dev)
fixed_mem_resource(dev, index++, pcie_config_base >> 10,
pcie_config_size >> 10, IORESOURCE_RESERVE);
}
-
- set_top_of_ram(usable_tomk * 1024);
}
static void mch_domain_set_resources(device_t dev)
diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c
index f11b19a..27562ea 100644
--- a/src/northbridge/intel/x4x/ram_calc.c
+++ b/src/northbridge/intel/x4x/ram_calc.c
@@ -17,6 +17,7 @@
#define __SIMPLE_DEVICE__
+#include <cbmem.h>
#include <commonlib/helpers.h>
#include <stdint.h>
#include <arch/io.h>
@@ -86,3 +87,9 @@ u8 decode_pciebar(u32 *const base, u32 *const len)
*len = max_buses << 20;
return 1;
}
+
+void *cbmem_top(void)
+{
+ u32 ramtop = pci_read_config32(PCI_DEV(0,0,0), D0F0_TSEG);
+ return (void*)(ramtop);
+}
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