[coreboot-gerrit] Patch set updated for coreboot: soc/apollolake: Read PCIe CLKREQ pin mapping from devicetree

[Alexandru Gagniuc (mr.nuke.me@gmail.com)]

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13407

-gerrit

commit 765140891a0a7d15a24846f014652058a52e704f
Author: Alexandru Gagniuc <alexandrux.gagniuc at intel.com>
Date:   Fri Jan 15 10:40:24 2016 -0800

    soc/apollolake: Read PCIe CLKREQ pin mapping from devicetree
    
    The corect CLKREQ signal to PCIe root port mapping is needed in order
    for PCIe devices to enumerate. This mapping is board-specific, so get
    it from devicetree.
    
    Change-Id: I0a5057274b84c41ef529052c5967ea4321e5f450
    Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc at intel.com>
---
 src/soc/intel/apollolake/chip.c | 22 ++++++++++++++++++++++
 src/soc/intel/apollolake/chip.h | 32 ++++++++++++++++++++++++++++++++
 2 files changed, 54 insertions(+)

diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 180cfc1..630df3e 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -18,6 +18,8 @@
 #include <device/pci.h>
 #include <fsp/api.h>
 
+#include "chip.h"
+
 static void pci_domain_set_resources(device_t dev)
 {
        assign_resources(dev->link_list);
@@ -60,6 +62,26 @@ static void soc_init(void *data)
 	fsp_silicon_init();
 }
 
+void platform_fsp_silicon_init_params_cb(struct SILICON_INIT_UPD *silupd)
+{
+	static struct soc_intel_apollolake_config *cfg;
+
+	struct device *dev = dev_find_slot(0, 0);
+	if (!dev && !dev->chip_info) {
+		printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
+		return;
+	}
+
+	cfg = dev->chip_info;
+
+	silupd->PcieRpClkReqNumber[0] = cfg->pcie_rp0_clkreq_pin;
+	silupd->PcieRpClkReqNumber[1] = cfg->pcie_rp1_clkreq_pin;
+	silupd->PcieRpClkReqNumber[2] = cfg->pcie_rp2_clkreq_pin;
+	silupd->PcieRpClkReqNumber[3] = cfg->pcie_rp3_clkreq_pin;
+	silupd->PcieRpClkReqNumber[4] = cfg->pcie_rp4_clkreq_pin;
+	silupd->PcieRpClkReqNumber[5] = cfg->pcie_rp5_clkreq_pin;
+}
+
 struct chip_operations soc_intel_apollolake_ops = {
 	CHIP_NAME("Intel Apollolake SOC")
 	.enable_dev = &enable_dev,
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
new file mode 100644
index 0000000..026fdda
--- /dev/null
+++ b/src/soc/intel/apollolake/chip.h
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _SOC_APOLLOLAKE_CHIP_H_
+#define _SOC_APOLLOLAKE_CHIP_H_
+
+#define CLKREQ_DISABLED		0xf
+
+struct soc_intel_apollolake_config {
+	/*
+	 * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has
+	 * four CLKREQ inputs, but six root ports. Root ports without an
+	 * associated CLKREQ signal must be marked with "CLKREQ_DISABLED"
+	 */
+	uint8_t pcie_rp0_clkreq_pin;
+	uint8_t pcie_rp1_clkreq_pin;
+	uint8_t pcie_rp2_clkreq_pin;
+	uint8_t pcie_rp3_clkreq_pin;
+	uint8_t pcie_rp4_clkreq_pin;
+	uint8_t pcie_rp5_clkreq_pin;
+};
+
+#endif	/* _SOC_APOLLOLAKE_CHIP_H_ */