[coreboot-gerrit] Patch set updated for coreboot: drivers/intel/fsp2_0: Define tentative coreboot <-> FSP 2.0 API

[Alexandru Gagniuc (mr.nuke.me@gmail.com)]

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13335

-gerrit

commit d2533c99e44a8ae10127847b531421876bd68a99
Author: Alexandru Gagniuc <alexandrux.gagniuc at intel.com>
Date:   Thu Oct 29 17:48:14 2015 -0700

    drivers/intel/fsp2_0: Define tentative coreboot <-> FSP 2.0 API
    
    This defines the initial API between coreboot and FSP 2.0. The design
    attempts to abstract from the common code as much of the FSP details
    as possible.
    
    Change-Id: I57f629eecb259cbe10c489d5dae56afe260b5197
    Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc at intel.com>
---
 src/drivers/intel/fsp2_0/include/fsp/api.h | 43 ++++++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)

diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h
new file mode 100644
index 0000000..75dcffe
--- /dev/null
+++ b/src/drivers/intel/fsp2_0/include/fsp/api.h
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _FSP2_0_API_H_
+#define _FSP2_0_API_H_
+
+#include "FspUpdVpd.h"
+
+enum fsp_status {
+	FSP_SUCCESS = 0x00000000,
+	FSP_INVALID_PARAMETER = 0x80000002,
+	FSP_UNSUPPORTED = 0x80000003,
+	FSP_NOT_READY = 0x80000006,
+	FSP_DEVICE_ERROR = 0x80000007,
+	FSP_OUT_OF_RESOURCES = 0x80000009,
+	FSP_VOLUME_CORRUPTED = 0x8000000a,
+	FSP_NOT_FOUND = 0x8000000a,
+	FSP_TIMEOUT = 0x80000012,
+	FSP_ABORTED = 0x80000015,
+	FSP_INCOMPATIBLE_VERSION = 0x80000010,
+	FSP_SECURITY_VIOLATION = 0x8000001a,
+	FSP_CRC_ERROR = 0x8000001b,
+};
+
+/* Main FSP stages */
+enum fsp_status fsp_memory_init(void);
+enum fsp_status fsp_silicon_init(void);
+enum fsp_status fsp_notify(void);
+
+/* Callbacks for updating stage-specific parameters */
+void platform_fsp_memory_init_params_cb(struct MEMORY_INIT_UPD *memupd);
+void platform_fsp_silicon_init_params_cb(struct SILICON_INIT_UPD *silupd);
+
+#endif /* _FSP2_0_API_H_ */