[coreboot-gerrit] Patch set updated for coreboot: soc/apollolake: Rename cpu.c to tsc_freq.c, add copyright header

[Alexandru Gagniuc (mr.nuke.me@gmail.com)]

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13343

-gerrit

commit 7bf063658166e8ff274ea1b7e6861b010be3b329
Author: Alexandru Gagniuc <alexandrux.gagniuc at intel.com>
Date:   Thu Nov 5 11:14:51 2015 -0800

    soc/apollolake: Rename cpu.c to tsc_freq.c, add copyright header
    
    To be consistent with other platforms, cpu.c should contain the
    ramstage CPU drivers. Since other Intel SOCs use tsc_freq.c for the
    same purpose we used cpu.c, rename it accordingly.
    
    Change-Id: I4ce6d9d9b37cc28d3cd74f7dd795718a07c6e8d4
    Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc at intel.com>
---
 src/soc/intel/apollolake/Makefile.inc |  6 +++---
 src/soc/intel/apollolake/cpu.c        |  9 ---------
 src/soc/intel/apollolake/tsc_freq.c   | 21 +++++++++++++++++++++
 3 files changed, 24 insertions(+), 12 deletions(-)

diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 63c39b3..ca81304 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -8,26 +8,26 @@ subdirs-y += ../../../cpu/x86/smm
 subdirs-y += ../../../cpu/x86/tsc
 
 bootblock-y += bootblock/bootblock_car.c
-bootblock-y += cpu.c
 bootblock-y += gpio.c
 bootblock-y += bootblock/cache_as_ram.S
 bootblock-y += bootblock/early_chipset_config.S
 bootblock-y += mmap_boot.c
+bootblock-y += tsc_freq.c
 bootblock-y += uart_early.c
 
 cpu_incs-y += $(src)/soc/intel/apollolake/romstage/entry.inc
-romstage-y += cpu.c
 romstage-y += gpio.c
 romstage-y += memmap.c
 romstage-y += mmap_boot.c
 romstage-y += romstage/romstage.c
+romstage-y += tsc_freq.c
 romstage-y += uart_early.c
 
 ramstage-y += chip.c
-ramstage-y += cpu.c
 ramstage-y += gpio.c
 ramstage-y += memmap.c
 ramstage-y += mmap_boot.c
+ramstage-y += tsc_freq.c
 ramstage-y += uart.c
 
 romstage-y += placeholders.c
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c
deleted file mode 100644
index e804697..0000000
--- a/src/soc/intel/apollolake/cpu.c
+++ /dev/null
@@ -1,9 +0,0 @@
-#include <cpu/x86/msr.h>
-#include <cpu/x86/tsc.h>
-#include <soc/cpu.h>
-
-unsigned long tsc_freq_mhz(void)
-{
-	msr_t msr = rdmsr(MSR_PLATFORM_INFO);
-	return (BASE_CLOCK_MHZ * ((msr.lo >> 8) & 0xff));
-}
diff --git a/src/soc/intel/apollolake/tsc_freq.c b/src/soc/intel/apollolake/tsc_freq.c
new file mode 100644
index 0000000..2e90ef2
--- /dev/null
+++ b/src/soc/intel/apollolake/tsc_freq.c
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <cpu/x86/msr.h>
+#include <cpu/x86/tsc.h>
+#include <soc/cpu.h>
+
+unsigned long tsc_freq_mhz(void)
+{
+	msr_t msr = rdmsr(MSR_PLATFORM_INFO);
+	return (BASE_CLOCK_MHZ * ((msr.lo >> 8) & 0xff));
+}