[coreboot-gerrit] Patch set updated for coreboot: drivers/intel/fsp2_0: Add functionality to decode FSP 2.0 headers

[Alexandru Gagniuc (mr.nuke.me@gmail.com)]

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13330

-gerrit

commit d3e6d3ff63ae1e9e62c6c19fe7b749745e9076e4
Author: Alexandru Gagniuc <alexandrux.gagniuc at intel.com>
Date:   Thu Oct 29 16:48:54 2015 -0700

    drivers/intel/fsp2_0: Add functionality to decode FSP 2.0 headers
    
    This adds the minimum code needed to interpret the information in FSP
    headers. Only the fields that are useful are being decoded.
    
    Change-Id: Iffbeed2db1b267fe08f7935b797d94469f65b48b
    Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc at intel.com>
---
 src/drivers/intel/fsp2_0/Makefile.inc              |  2 +
 src/drivers/intel/fsp2_0/include/fsp/info_header.h | 40 +++++++++++++
 src/drivers/intel/fsp2_0/util.c                    | 70 ++++++++++++++++++++++
 3 files changed, 112 insertions(+)

diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc
index c85b4bc..b6cb7cd 100644
--- a/src/drivers/intel/fsp2_0/Makefile.inc
+++ b/src/drivers/intel/fsp2_0/Makefile.inc
@@ -1,4 +1,6 @@
 
+romstage-y += util.c
+
 CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include
 
 cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += blobs/fsp-m.bin
diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h
new file mode 100644
index 0000000..1e88410
--- /dev/null
+++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _FSP2_0_INFO_HEADER_H_
+#define _FSP2_0_INFO_HEADER_H_
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <types.h>
+
+#define FSP_HDR_OFFSET			0x94
+#define FSP_HDR_LEN			0x48
+#define FSP_HDR_SIGNATURE		"FSPH"
+
+struct fsp_header {
+	uint32_t fsp_revision;
+	size_t image_size;
+	uintptr_t image_base;
+	size_t cfg_region_offset;
+	size_t cfg_region_size;
+	size_t notify_phase_entry_offset;
+	size_t memory_init_entry_offset;
+	size_t silicon_init_entry_offset;
+	char image_id[9];
+	uint8_t revision;
+};
+
+enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob);
+void fsp_print_header_info(const struct fsp_header *hdr);
+
+#endif /* _FSP2_0_INFO_HEADER_H_ */
diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c
new file mode 100644
index 0000000..4e1dbf3
--- /dev/null
+++ b/src/drivers/intel/fsp2_0/util.c
@@ -0,0 +1,70 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <fsp/info_header.h>
+#include <lib.h>
+#include <string.h>
+
+static bool looks_like_fsp_header(const uint8_t *raw_hdr)
+{
+	if (memcmp(raw_hdr, FSP_HDR_SIGNATURE, 4)) {
+		printk(BIOS_ALERT, "Did not find a valid FSP signature\n");
+		return false;
+	}
+
+	if (read32(raw_hdr + 4) != FSP_HDR_LEN) {
+		printk(BIOS_ALERT, "FSP header has invalid length\n");
+		return false;
+	}
+
+	return true;
+}
+
+enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob)
+{
+	const uint8_t *raw_hdr = fsp_blob;
+	raw_hdr += FSP_HDR_OFFSET;
+
+	if (!looks_like_fsp_header(raw_hdr))
+		return CB_ERR;
+
+	hdr->revision = read8(raw_hdr + 0x0b);
+	hdr->fsp_revision = read32(raw_hdr + 0x0c);
+	memcpy(hdr->image_id, raw_hdr + 0x10, 8);
+	hdr->image_id[8] = '\0';
+	hdr->image_size = read32(raw_hdr + 0x18);
+	hdr->image_base = read32(raw_hdr + 0x1c);
+	hdr->cfg_region_offset = read32(raw_hdr + 0x24);
+	hdr->cfg_region_size = read32(raw_hdr + 0x28);
+	hdr->notify_phase_entry_offset = read32(raw_hdr + 0x38);
+	hdr->memory_init_entry_offset = read32(raw_hdr + 0x3c);
+	hdr->silicon_init_entry_offset = read32(raw_hdr + 0x44);
+
+	return CB_SUCCESS;
+}
+
+void fsp_print_header_info(const struct fsp_header *hdr)
+{
+	printk(BIOS_DEBUG, "Revision %u, image ID: %s, base 0x%zx + 0x%zx\n",
+	       hdr->revision ,hdr->image_id, hdr->image_base, hdr->image_size);
+
+	printk(BIOS_DEBUG, "\tConfig region        0x%zx + 0x%zx\n",
+	       hdr->cfg_region_offset, hdr->cfg_region_size);
+	printk(BIOS_DEBUG, "\tMemory init offset   0x%zx\n"
+			   "\tSilicon init offset  0x%zx\n"
+			   "\tNotify phase offset  0x%zx\n",
+	       hdr->memory_init_entry_offset,
+	       hdr->silicon_init_entry_offset,
+	       hdr->notify_phase_entry_offset);
+}