[coreboot-gerrit] Patch set updated for coreboot: soc/apollolake: Add BAR setup and enables essential for raminit

[Alexandru Gagniuc (mr.nuke.me@gmail.com)]

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13324

-gerrit

commit 479226c17026fb79893da9fc42040152e6dfc883
Author: Andrey Petrov <andrey.petrov at intel.com>
Date:   Mon Oct 26 18:10:04 2015 -0700

    soc/apollolake: Add BAR setup and enables essential for raminit
    
    Change-Id: I884e677e607a14e9e88877a8e94e8518d473cf83
    Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
    Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc at intel.com>
---
 src/soc/intel/apollolake/bootblock/bootblock_car.c |  7 ++--
 src/soc/intel/apollolake/include/soc/iomap.h       | 26 +++++++++++++++
 src/soc/intel/apollolake/romstage/romstage.c       | 37 ++++++++++++++++++++++
 3 files changed, 67 insertions(+), 3 deletions(-)

diff --git a/src/soc/intel/apollolake/bootblock/bootblock_car.c b/src/soc/intel/apollolake/bootblock/bootblock_car.c
index 7dd359b..8d317a1 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock_car.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock_car.c
@@ -16,6 +16,7 @@
 #include <device/pci.h>
 #include <soc/bootblock.h>
 #include <soc/cpu.h>
+#include <soc/iomap.h>
 #include <soc/uart.h>
 
 static void disable_watchdog(void)
@@ -24,14 +25,14 @@ static void disable_watchdog(void)
 	device_t dev = PCI_DEV(0, 0xd, 1);
 
 	/* Open up an IO window */
-	pci_write_config16(dev, PCI_BASE_ADDRESS_4, 0x400);
+	pci_write_config16(dev, PCI_BASE_ADDRESS_4, ACPI_PMIO_BASE);
 	pci_write_config32(dev, PCI_COMMAND,
 			   PCI_COMMAND_MASTER | PCI_COMMAND_IO);
 
 	/* We don't have documentation for this bit, but it prevents reboots */
-	reg = inl(0x400 + 0x68);
+	reg = inl(ACPI_PMIO_BASE + 0x68);
 	reg |= 1 << 11;
-	outl(reg, 0x400 + 0x68);
+	outl(reg, ACPI_PMIO_BASE + 0x68);
 }
 
 static void call_romstage(void *entry)
diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h
new file mode 100644
index 0000000..09ae67d
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/iomap.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Andrey Petrov <andrey.petrov at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _SOC_APOLLOLAKE_IOMAP_H_
+#define _SOC_APOLLOLAKE_IOMAP_H_
+
+#define P2SB_BAR			0xd0000000
+#define MCH_BASE_ADDR			0xfed10000
+
+#define ACPI_PMIO_BASE			0x400
+#define  R_ACPI_PM1_TMR			0x8
+
+/* Accesses to these BARs are hardcoded in FSP */
+#define PMC_BAR0			0xfe042000
+#define PMC_BAR1			0xfe044000
+
+#endif /* _SOC_APOLLOLAKE_IOMAP_H_ */
diff --git a/src/soc/intel/apollolake/romstage/romstage.c b/src/soc/intel/apollolake/romstage/romstage.c
index f76476b..1bf94f4 100644
--- a/src/soc/intel/apollolake/romstage/romstage.c
+++ b/src/soc/intel/apollolake/romstage/romstage.c
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2015 Intel Corp.
  * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
+ * (Written by Andrey Petrov <andrey.petrov at intel.com> for Intel Corp.)
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -10,10 +11,44 @@
  * (at your option) any later version.
  */
 
+#include <arch/io.h>
 #include <console/console.h>
+#include <cpu/x86/msr.h>
+#include <device/pci_def.h>
+#include <soc/iomap.h>
 #include <soc/romstage.h>
 #include <soc/uart.h>
 
+/*
+ * Enables several BARs and devices which are needed for memory init
+ * - MCH_BASE_ADDR is needed in order to talk to the memory controller
+ * - PMC_BAR0 and PMC_BAR1 are used by FSP (with the base address hardcoded)
+ *   Once raminit is done, we can safely let the allocator re-assign them
+ * - HPET is enabled because FSP wants to store a pointer to global data in the
+ *   HPET comparator register
+ */
+static void soc_early_romstage_init(void)
+{
+	device_t pmc = PCI_DEV(0, 13, 1);
+
+	/* Set MCH base address */
+	pci_write_config32(PCI_DEV(0, 0, 0), 0x48, MCH_BASE_ADDR);
+
+	/* Set PMC base address */
+	pci_write_config32(pmc, PCI_BASE_ADDRESS_0, PMC_BAR0);
+	pci_write_config32(pmc, PCI_BASE_ADDRESS_1, 0);	/* 64-bit BAR */
+	pci_write_config32(pmc, PCI_BASE_ADDRESS_2, PMC_BAR1);
+	pci_write_config32(pmc, PCI_BASE_ADDRESS_3, 0);	/* 64-bit BAR */
+
+	/* PMIO BAR4 was already set in bootblock, hence the COMMAND_IO below */
+	pci_write_config32(pmc, PCI_COMMAND,
+				PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
+				PCI_COMMAND_MASTER);
+
+	/* Enable decoding for HPET */
+	pci_write_config32(PCI_DEV(0, 13, 0), 0x60, 1<<7);
+}
+
 asmlinkage void romstage_entry(void)
 {
 	/* Be careful. Bootblock might already have initialized the console */
@@ -24,6 +59,8 @@ asmlinkage void romstage_entry(void)
 
 	printk(BIOS_DEBUG, "Starting romstage...\n");
 
+	soc_early_romstage_init();
+
 	/* This function must not return */
 	while(1)
 		;