[coreboot-gerrit] Patch set updated for coreboot: drivers/intel/fsp2_0: Add initial FspUpdVpd.h header
Alexandru Gagniuc (mr.nuke.me@gmail.com)
gerrit at coreboot.org
Tue Jan 26 17:36:01 CET 2016
Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13332
-gerrit
commit 63dc0f404de6511abe352b0f7b5bd01d9b527471
Author: Alexandru Gagniuc <alexandrux.gagniuc at intel.com>
Date: Mon Nov 2 13:40:06 2015 -0800
drivers/intel/fsp2_0: Add initial FspUpdVpd.h header
This is the header which defines the parameter interfaceof the FSP
blob. Since thi is specific to the FSP blob, and is subject to change,
it is added in a separate commit.
Change-Id: I7b7bb77817ec0e757a569f90d0248d50df5e34c8
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc at intel.com>
---
src/drivers/intel/fsp2_0/include/fsp/FspUpdVpd.h | 447 +++++++++++++++++++++++
1 file changed, 447 insertions(+)
diff --git a/src/drivers/intel/fsp2_0/include/fsp/FspUpdVpd.h b/src/drivers/intel/fsp2_0/include/fsp/FspUpdVpd.h
new file mode 100644
index 0000000..441e43a
--- /dev/null
+++ b/src/drivers/intel/fsp2_0/include/fsp/FspUpdVpd.h
@@ -0,0 +1,447 @@
+/** @file
+
+Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPUPDVPD_H__
+#define __FSPUPDVPD_H__
+
+#define MAX_CHANNELS_NUM 2
+#define MAX_DIMMS_NUM 2
+
+struct DIMM_INFO {
+ uint8_t DimmId;
+ uint32_t SizeInMb;
+} __attribute__((packed));
+
+struct CHANNEL_INFO {
+ uint8_t ChannelId;
+ uint8_t DimmCount;
+ struct DIMM_INFO DimmInfo[MAX_DIMMS_NUM];
+} __attribute__((packed));
+
+struct FSP_SMBIOS_MEMORY_INFO {
+ uint8_t Revision;
+ uint16_t DataWidth;
+ /** As defined in SMBIOS 3.0 spec
+ Section 7.18.2 and Table 75
+ **/
+ uint8_t MemoryType;
+ uint16_t MemoryFrequencyInMHz;
+ /** As defined in SMBIOS 3.0 spec
+ Section 7.17.3 and Table 72
+ **/
+ uint8_t ErrorCorrectionType;
+ uint8_t ChannelCount;
+ struct CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM];
+} __attribute__((packed));
+
+typedef union{
+ uint32_t padCnf0;
+ struct {
+ uint32_t GPIOTxState:1; ///< 0 GPIO TX State
+ uint32_t GPIORxState:1; ///< 1 GPIO RX State, RO
+ uint32_t Reserved1:6; ///< 2-7 Reserved, RO
+ uint32_t GPIORxTxDis:2; ///< 8-9 GPIO RX Disable[9], GPIO TX Disable[8]
+ uint32_t PMode:3; ///< 10-12 Pad Mode, 0h = GPIO Controller controls the Pad; 1h = Native Function 1, if applicable, controls the pad; 2h = Native Function 2, if applicable, controls the pad, etc.
+ uint32_t Reserved2:4; ///< 13-16 Reserved, RO
+ uint32_t GPIRout:4; ///< 17-20 Route to IOxAPIC[20], SCI[19], SMI[18], NMI[17]
+ uint32_t RXTXEnCfg:2; ///< 21-22 RX/TX Enable Config (RXTXEnCfg) RO
+ uint32_t RXINV:1; ///< 23 RX Invert, 0 = No inversion; 1 = Inversion
+ uint32_t PreGfRXSel:1; ///< 24 Pre Glitch Filter Stage RX Pad State Select, RO, not support in BXT
+ uint32_t RxEvCfg:2; ///< 25-26 0h = Level 1h = Edge (RxInv=0 for rising edge; 1 for falling edge), 2h = Disabled ,3h = Either rising edge or falling edge
+ uint32_t Reserved3:1; ///< 27 RO
+ uint32_t RXRAW1:1; ///< 28 Override the RX to 1
+ uint32_t RXPadStSel:1; ///< 29 RX Pad State Select
+ uint32_t PadRstCfg:2; ///< 30-31 Pad Reset Config
+ } r;
+} BL_CONF_PAD0;
+
+typedef union{
+ uint32_t padCnf1;
+ struct {
+ uint32_t IntSel:7; ///< 0-6 Interrupt Select. RO
+ uint32_t Reserved:1; ///< 7 Reserved.
+ uint32_t IOSTerm:2; ///< 8-9 I/O Standby Termination (IOSTerm) RW
+ uint32_t Term:4; ///< 10-13 Termination,
+ ///< 0 000: none;0 010: 5k wpd;0 100: 20k wpd;1 000: none;1 001: 1k wpu;1 011: 2k wpu;1 010: 5k wpu;
+ ///< 1 100: 20k wpu;1 101: 1k & 2k wpu;1 111: (optional) Native controller selected by Pad Mode controls the Termination
+ uint32_t IOSState:4; ///< 14-17 I/O Standby State, I/O Standby is not implemented in BXT, RW
+ uint32_t CFIOPadCfg:14; ///< 18-31 For BXT, this is done thru Family Register if necessary. RO
+ } r;
+} BL_CONF_PAD1;
+
+struct BL_GPIO_PAD_INIT {
+ BL_CONF_PAD0 padConfg0;
+ BL_CONF_PAD1 padConfg1;
+ uint8_t Community;
+ uint16_t MMIO_ADDRESS;
+ bool HostSw;
+ bool WakeEnabled; ///< Wake enable for direct IRQ pin
+ wchar_t *pad_name; ///< GPIO Pin Name for debug purpose
+} __attribute__((packed));
+
+
+
+struct TEMP_RAM_INIT_UPD {
+/** Offset 0x0020
+**/
+ uint64_t Signature;
+/** Offset 0x0028
+**/
+ uint8_t Revision;
+/** Offset 0x0029
+**/
+ uint8_t UnusedUpdSpace0[83];
+/** Offset 0x007C
+**/
+ uint32_t ReservedTempRamInitUpd;
+} __attribute__((packed));
+
+struct MEMORY_INIT_UPD {
+/** Offset 0x0080
+**/
+ uint64_t Signature;
+/** Offset 0x0088
+**/
+ uint8_t Revision;
+/** Offset 0x0089
+**/
+ uint8_t UnusedUpdSpace1[7];
+/** Offset 0x0090
+ Debug Serial Port Base
+ Debug serial port resource base address, either I/O or MMIO base.
+**/
+ uint32_t SerialDebugPortAddress;
+/** Offset 0x0094
+ Debug Serial Port Type
+ Debug serial port resource type. NONE means no serial port support.
+**/
+ uint8_t SerialDebugPortType;
+/** Offset 0x0095
+ Serial Port Debug Device
+ Select active serial port device. For SOC UART devices,'Debug Serial Port Base' options will be ignored.
+**/
+ uint8_t SerialDebugPortDevice;
+/** Offset 0x0096
+ Debug Serial Port Stride Size
+ Debug serial port register map stride size.
+**/
+ uint8_t SerialDebugPortStrideSize;
+/** Offset 0x0097
+**/
+ uint8_t ReservedUpd1;
+/** Offset 0x0098
+ Memory FastBootSupport
+ MRC Fast Boot Support
+**/
+ uint8_t MrcFastBoot;
+/** Offset 0x0099
+**/
+ uint8_t UnusedUpdSpace2[7];
+/** Offset 0x00A0
+ Memory EccSupport
+ ECC Support
+**/
+ uint8_t EccSupport;
+/** Offset 0x00A1
+ Memory DdrFreqLimit
+ DDR Freq Limit
+**/
+ uint8_t DdrFreqLimit;
+/** Offset 0x00A2
+ Memory MaxTolud
+ MaxTolud
+**/
+ uint32_t MaxTolud;
+/** Offset 0x00A6
+ MrcDebugMsgLevel
+ Set MRC DebugMsg Level
+**/
+ uint8_t MrcDebugMsgLevel;
+/** Offset 0x00A7
+ Integrated Graphics Device
+ Enable : Enable Integrated Graphics Device (IGD) when selected as the Primary Video Adaptor. Disable: Alwarys disable IGD
+**/
+ uint8_t Igd;
+/** Offset 0x00A8
+ DVMT Pre-Allocated
+ Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal Graphics Device
+**/
+ uint8_t IgdDvmt50PreAlloc;
+/** Offset 0x00A9
+ Aperture Size
+ Select the Aperture Size.
+**/
+ uint8_t IgdApertureSize;
+/** Offset 0x00AA
+ GTT Size
+ Select the GTT Size.
+**/
+ uint8_t GTTSize;
+/** Offset 0x00AB
+ Primary Display
+ Select which of IGD/PCI Graphics device should be Primary Display.
+**/
+ uint8_t PrimaryVideoAdaptor;
+/** Offset 0x00AC
+**/
+ uint8_t PmSupport;
+/** Offset 0x00AD
+**/
+ uint8_t EnableRenderStandby;
+/** Offset 0x00AE
+**/
+ uint8_t PavpEnable;
+/** Offset 0x00AF
+**/
+ uint8_t SataEnable;
+/** Offset 0x00B0
+ Enable SATA
+ Enable/disable SATA controller.
+**/
+ uint8_t EnableSata;
+/** Offset 0x00B1
+ SATA Mode
+ Select SATA controller working mode.
+**/
+ uint8_t SataMode;
+/** Offset 0x00B2
+ Enable SATA
+ Enable/disable SATA controller.
+**/
+ uint8_t SataSalpSupport;
+/** Offset 0x00B3
+ Enable SATA ports
+ Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, and so on.
+**/
+ uint8_t SataPortsEnable[2];
+/** Offset 0x00B5
+ Enable SATA DEVSLP Feature
+ Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each port, byte0 for port0, byte1 for port1, and so on.
+**/
+ uint8_t SataPortsDevSlp[2];
+/** Offset 0x00B7
+ Enable PCIE RP
+ Enable/disable PCIE Root Ports. 0: disable, 1: enable. One byte for each port, byte0 for port1, byte1 for port2, and so on.
+**/
+ uint8_t PcieRpEnable[6];
+/** Offset 0x00BD
+ Configure CLKREQ Number
+ Configure Root Port CLKREQ Number if CLKREQ is supported. Each value in arrary can be between 0-6. One byte for each port, byte0 for port1, byte1 for port2, and so on.
+**/
+ uint8_t PcieRpClkReqNumber[6];
+/** Offset 0x00C3
+ Enable USB2 ports
+ Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on.
+**/
+ uint8_t PortUsb20Enable[8];
+/** Offset 0x00CB
+ Enable USB3 ports
+ Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on.
+**/
+ uint8_t PortUsb30Enable[6];
+/** Offset 0x00D1
+ Enable XHCI SSIC Eanble
+ Enable/disable XHCI SSIC port.
+**/
+ uint8_t SsicPortEnable;
+/** Offset 0x00D2
+ Enable SMBus
+ Enable/disable SMBus controller.
+**/
+ uint8_t SmbusEnable;
+/** Offset 0x00D3
+**/
+ uint8_t UnusedUpdSpace3[13];
+/** Offset 0x00E0
+**/
+ uint8_t IspEn;
+/** Offset 0x00E1
+**/
+ uint8_t IspAcpiMode;
+/** Offset 0x00E2
+**/
+ uint32_t AdditionalFvBase;
+/** Offset 0x00E6
+**/
+ uint8_t UnusedUpdSpace4[122];
+/** Offset 0x0160
+**/
+ uint32_t ObbLoadingBase;
+/** Offset 0x0164
+**/
+ uint32_t ObbFlashBase;
+/** Offset 0x0168
+**/
+ uint32_t ObbFlashSize;
+/** Offset 0x016C
+**/
+ uint8_t UnusedUpdSpace5[20];
+/** Offset 0x0180
+**/
+ uint8_t ObbFileName[16];
+/** Offset 0x0190
+**/
+ uint8_t UnusedUpdSpace6[48];
+/** Offset 0x01C0
+**/
+ struct BL_GPIO_PAD_INIT* GpioPadInitTablePtr;
+/** Offset 0x01C4
+**/
+ uint8_t UnusedUpdSpace7[56];
+/** Offset 0x01FC
+**/
+ uint32_t ReservedMemoryInitUpd;
+} __attribute__((packed));
+
+struct SILICON_INIT_UPD {
+/** Offset 0x0200
+**/
+ uint64_t Signature;
+/** Offset 0x0208
+**/
+ uint8_t Revision;
+/** Offset 0x0209
+**/
+ uint8_t UnusedUpdSpace8[7];
+/** Offset 0x0210
+ Logo Pointer
+ Points to PEI Display Logo Image
+**/
+ uint32_t LogoPtr;
+/** Offset 0x0214
+ Logo Size
+ Size of PEI Display Logo Image
+**/
+ uint32_t LogoSize;
+/** Offset 0x0218
+ Graphics Configuration Ptr
+ Points to VBT
+**/
+ uint32_t GraphicsConfigPtr;
+/** Offset 0x021C
+ Enable HD Audio DSP
+ Enable/disable HD Audio DSP feature.
+**/
+ uint8_t DspEnable;
+/** Offset 0x021D
+ Select HDAudio IoBuffer Ownership
+ Select HDAudio IoBuffer Ownership.
+**/
+ uint8_t IoBufferOwnership;
+/** Offset 0x021E
+ BXT PlatformType
+ BXT PlatformType.
+**/
+ uint8_t PlatformType;
+/** Offset 0x021F
+ DynSR
+ Enable/disable DynSR feature.
+**/
+ uint8_t DynSR;
+/** Offset 0x0220
+**/
+ uint8_t UnusedUpdSpace9[20];
+/** Offset 0x0234
+**/
+ uint8_t ReservedSiliconInitUpd[292];
+} __attribute__((packed));
+
+#define FSP_UPD_SIGNATURE 0x2444505554584224 /* '$BXTUPD$' */
+#define FSP_TEMP_RAM_INIT_UPD_SIGNATURE 0x24445055504D5424 /* '$TMPUPD$' */
+#define FSP_MEMORY_INIT_UPD_SIGNATURE 0x244450554D454D24 /* '$MEMUPD$' */
+#define FSP_SILICON_INIT_UPD_SIGNATURE 0x244450555F495324 /* '$SI_UPD$' */
+
+struct UPD_DATA_REGION {
+/** Offset 0x0000
+**/
+ uint64_t Signature;
+/** Offset 0x0008
+**/
+ uint8_t Revision;
+/** Offset 0x0009
+**/
+ uint8_t ReservedUpd0[7];
+/** Offset 0x0010
+**/
+ uint32_t TempRamInitUpdOffset;
+/** Offset 0x0014
+**/
+ uint32_t MemoryInitUpdOffset;
+/** Offset 0x0018
+**/
+ uint32_t SiliconInitUpdOffset;
+/** Offset 0x001C
+**/
+ uint32_t ReservedUpd1;
+/** Offset 0x0020
+**/
+ struct TEMP_RAM_INIT_UPD TempRamInitUpd;
+/** Offset 0x0080
+**/
+ struct MEMORY_INIT_UPD MemoryInitUpd;
+/** Offset 0x0200
+**/
+ struct SILICON_INIT_UPD SiliconInitUpd;
+/** Offset 0x0358
+**/
+ uint8_t UnusedUpdSpace10[166];
+/** Offset 0x03FE
+**/
+ uint16_t RegionTerminator;
+} __attribute__((packed));
+
+#define FSP_IMAGE_ID 0x2450534654584224 /* '$BXTFSP$' */
+#define FSP_IMAGE_REV 0x01010000
+
+struct VPD_DATA_REGION {
+/** Offset 0x0000
+**/
+ uint64_t PcdVpdRegionSign;
+/** Offset 0x0008
+ PcdImageRevision
+**/
+ uint32_t PcdImageRevision;
+/** Offset 0x000C
+**/
+ uint32_t PcdUpdRegionOffset;
+/** Offset 0x0010
+**/
+ uint32_t PcdUpdRegionSize;
+/** Offset 0x0014
+**/
+ uint64_t UnusedVpdSpace0;
+/** Offset 0x001C
+**/
+ uint32_t PcdVpdReserved;
+} __attribute__((packed));
+
+#endif
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