[coreboot-gerrit] Patch set updated for coreboot: soc/apollolake: Add enable bit for MCH BAR

[Alexandru Gagniuc (mr.nuke.me@gmail.com)]

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13325

-gerrit

commit bc805efa1b4890356135b0ec611d7365b7bf4226
Author: Andrey Petrov <andrey.petrov at intel.com>
Date:   Wed Oct 28 17:29:42 2015 -0700

    soc/apollolake: Add enable bit for MCH BAR
    
    Change-Id: Iac8f2f819126401f470caa688600824ccc2edad9
    Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
 src/soc/intel/apollolake/romstage/romstage.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/soc/intel/apollolake/romstage/romstage.c b/src/soc/intel/apollolake/romstage/romstage.c
index 38f4e85..a0d582d 100644
--- a/src/soc/intel/apollolake/romstage/romstage.c
+++ b/src/soc/intel/apollolake/romstage/romstage.c
@@ -32,8 +32,8 @@ static void soc_early_romstage_init(void)
 	msr_t msr;
 	device_t pmc = PCI_DEV(0, 13, 1);
 
-	/* Set MCH base address */
-	pci_write_config32(PCI_DEV(0, 0, 0), 0x48, MCH_BASE_ADDR);
+	/* Set MCH base address and enable bit */
+	pci_write_config32(PCI_DEV(0, 0, 0), 0x48, MCH_BASE_ADDR | 1);
 
 	/* Set PMC base address */
 	pci_write_config32(pmc, PCI_BASE_ADDRESS_0, PMC_BAR0);