[coreboot-gerrit] Patch set updated for coreboot: mb/intel/d510mo: Use SATA AHCI by default

[Damien Zammit (damien@zamaudio.com)]

Damien Zammit (damien at zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13454

-gerrit

commit 96c4d6176cb89c48b9dbfe5c6e343a50bd045d9a
Author: Damien Zammit <damien at zamaudio.com>
Date:   Tue Jan 26 14:03:37 2016 +1100

    mb/intel/d510mo: Use SATA AHCI by default
    
    Change-Id: I6f9772c5bcf9a50dfbc3d1cfaeb79f4454d1fb27
    Signed-off-by: Damien Zammit <damien at zamaudio.com>
---
 src/mainboard/intel/d510mo/devicetree.cb | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/intel/d510mo/devicetree.cb b/src/mainboard/intel/d510mo/devicetree.cb
index df5a0f9..c0f38de 100644
--- a/src/mainboard/intel/d510mo/devicetree.cb
+++ b/src/mainboard/intel/d510mo/devicetree.cb
@@ -38,10 +38,8 @@ chip northbridge/intel/pineview		# Northbridge
       register "pirqf_routing" = "0x0b"
       register "pirqg_routing" = "0x0b"
       register "pirqh_routing" = "0x0b"
-      register "ide_legacy_combined" = "0x1"
-      register "ide_enable_primary" = "0x1"
-      register "ide_enable_secondary" = "0x0"
-      register "sata_ahci" = "0x0"
+      register "sata_ahci" = "0x1"
+      register "sata_ports_implemented" = "0x3"
       register "gpe0_en" = "0x20000040"
 
       device pci 1b.0 on end		# Audio