[coreboot-gerrit] Patch set updated for coreboot: mb/intel/d510mo: Use native gfx initialization

[Damien Zammit (damien@zamaudio.com)]

Damien Zammit (damien at zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13034

-gerrit

commit 8485ef57bae58f6abbca80c9c680f38e94c74524
Author: Damien Zammit <damien at zamaudio.com>
Date:   Tue Jan 26 13:55:43 2016 +1100

    mb/intel/d510mo: Use native gfx initialization
    
    Change-Id: Ic4de7a762e90b379be3814afc61467e1cd099215
    Signed-off-by: Damien Zammit <damien at zamaudio.com>
---
 src/mainboard/intel/d510mo/Kconfig       |  2 ++
 src/mainboard/intel/d510mo/devicetree.cb | 10 ++++++++--
 src/mainboard/intel/d510mo/mainboard.c   |  4 +++-
 3 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/intel/d510mo/Kconfig b/src/mainboard/intel/d510mo/Kconfig
index 7981f92..7184665 100644
--- a/src/mainboard/intel/d510mo/Kconfig
+++ b/src/mainboard/intel/d510mo/Kconfig
@@ -23,6 +23,8 @@ config BOARD_SPECIFIC_OPTIONS
 	select SUPERIO_WINBOND_W83627THG
 	select HAVE_ACPI_TABLES
 	select BOARD_ROMSIZE_KB_1024
+	select MAINBOARD_HAS_NATIVE_VGA_INIT
+	select INTEL_INT15
 
 config MAX_CPUS
 	int
diff --git a/src/mainboard/intel/d510mo/devicetree.cb b/src/mainboard/intel/d510mo/devicetree.cb
index c6f39a0..df5a0f9 100644
--- a/src/mainboard/intel/d510mo/devicetree.cb
+++ b/src/mainboard/intel/d510mo/devicetree.cb
@@ -15,14 +15,20 @@
 #
 
 chip northbridge/intel/pineview		# Northbridge
+  register "gfx.use_spread_spectrum_clock" = "0"
+  register "use_crt" = "1"
+  register "use_lvds" = "0"
+
   device cpu_cluster 0 on		# APIC cluster
     chip cpu/intel/socket_FCBGA559	# CPU
       device lapic 0 on end		# APIC
     end
   end
-  device domain 0 on		# PCI domain
+  device domain 0 on			# PCI domain
     device pci 0.0 on end		# Host Bridge
-    device pci 2.0 off end		# Integrated graphics controller
+    device pci 1.0 off end		# PEG
+    device pci 2.0 on end		# Integrated graphics controller
+    device pci 2.1 on end		# Integrated graphics controller 2
     chip southbridge/intel/i82801gx	# Southbridge
       register "pirqa_routing" = "0x0b"
       register "pirqb_routing" = "0x0b"
diff --git a/src/mainboard/intel/d510mo/mainboard.c b/src/mainboard/intel/d510mo/mainboard.c
index 94bee7e..4f0f32b 100644
--- a/src/mainboard/intel/d510mo/mainboard.c
+++ b/src/mainboard/intel/d510mo/mainboard.c
@@ -18,10 +18,12 @@
 #include <device/pci_ops.h>
 #include <pc80/mc146818rtc.h>
 #include <device/pci.h>
+#include <drivers/intel/gma/int15.h>
 
 static void mainboard_enable(device_t dev)
 {
-	dev->ops->init = NULL;
+	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,
+		GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_CRT, 0);
 }
 
 struct chip_operations mainboard_ops = {