[coreboot-gerrit] Patch set updated for coreboot: x86 Docs: Add the FSP Binary
Leroy P Leahy (leroy.p.leahy@intel.com)
gerrit at coreboot.org
Tue Jan 26 02:57:48 CET 2016
Leroy P Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13442
-gerrit
commit 761e516d0c039c651bfbb664eaa3fbe24377650b
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date: Mon Jan 25 11:10:41 2016 -0800
x86 Docs: Add the FSP Binary
Document how to add the FSP binary to the SPI flash image.
BRANCH=none
BUG=None
TEST=None
Change-Id: I51b16600ea69853240282ac2eb0d84935b8e2a71
Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>
---
Documentation/x86Development.html | 1 +
Documentation/x86FSP1_1.html | 13 +++++++
Documentation/x86SoC.html | 71 +++++++++++++++++++++++++++++++++++++++
3 files changed, 85 insertions(+)
diff --git a/Documentation/x86Development.html b/Documentation/x86Development.html
index 8cd697f..852e1f3 100644
--- a/Documentation/x86Development.html
+++ b/Documentation/x86Development.html
@@ -44,6 +44,7 @@
<li>Get result to start <a target="_blank" href="x86SoC.html#Descriptor">booting</a></li>
<li><a target="_blank" href="x86SoC.html#EarlyDebug">Early Debug</a></li>
<li>Implement and debug the <a target="_blank" href="x86SoC.html#Bootblock">bootblock</a> code</li>
+ <li>Implement and debug the call to <a target="_blank" href="x86SoC.html#TempRamInit">TempRamInit</a></li>
</ol>
diff --git a/Documentation/x86FSP1_1.html b/Documentation/x86FSP1_1.html
index 52ff374..7a200b0 100644
--- a/Documentation/x86FSP1_1.html
+++ b/Documentation/x86FSP1_1.html
@@ -14,6 +14,7 @@
</p>
<ol>
<li><a href="#RequiredFiles">Required Files</a></li>
+ <li>Add the <a href="#FspBinary">FSP Binary File</a> to the Coreboot File System</li>
</ol>
@@ -39,6 +40,18 @@
<hr>
+<h1><a name="FspBinary">Add the FSP Binary File to Coreboot File System</a></h1>
+<p>
+ Add the FSP binary to the coreboot flash image using the following command:
+</p>
+<pre><code>util/cbfstool/cbfstool build/coreboot.rom add -t fsp -n fsp.bin -b <base address> -f fsp.bin</code></pre>
+<p>
+ This command relocates the FSP binary to the 4K byte aligned location in CBFS so that the
+ FSP code for TempRamInit may be executed in place.
+</p>
+
+
+<hr>
<p>Modified: 25 January 2016</p>
</body>
</html>
\ No newline at end of file
diff --git a/Documentation/x86SoC.html b/Documentation/x86SoC.html
index 5eab50d..ebd1ca7 100644
--- a/Documentation/x86SoC.html
+++ b/Documentation/x86SoC.html
@@ -18,6 +18,7 @@
<li><a href="#Descriptor">Start Booting</a></li>
<li><a href="#EarlyDebug">Early Debug</a></li>
<li><a href="#BootBlock">Bootblock</a></li>
+ <li><a href="#TempRamInit">TempRamInit</a></li>
</ol>
@@ -181,6 +182,76 @@ mv build/coreboot.rom.new build/coreboot.rom
<hr>
+<h1><a name="TempRamInit">TempRamInit</a></h1>
+<p>
+ Enable the call to TempRamInit using the following steps:
+</p>
+<ol>
+ <li>Edit the src/soc/<Vendor>/<Chip Family>/Kconfig file
+ <ol type="A">
+ <li>Add "select USE_GENERIC_FSP_CAR_INC" to enable the use of
+ <a target="_blank" href="https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2015.07/src/drivers/intel/fsp1_1/cache_as_ram.inc">src/drivers/intel/fsp1_1/cache_as_ram.inc</a>
+ </li>
+ <li>Add "select SOC_INTEL_COMMON" to enable the use of the files from
+ <a target="_blank" href="https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2015.07/src/soc/intel/common">src/soc/intel/common</a>
+ specifically building util.c
+ </li>
+ </ol>
+ </li>
+ <li>Debug the result until port 0x80 outputs
+ <ol type="A">
+ <li>0x90: <a target="_blank" href="https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2015.07/src/include/console/post_codes.h#209">POST_FSP_TEMP_RAM_INIT</a>
+ - Just before calling
+ <a target="_blank" href="https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2015.07/src/drivers/intel/fsp1_1/cache_as_ram.inc#90">TempRamInit</a>
+ </li>
+ <li>Alternating 0xba and 0x01 - The FSP image was not found</li>
+ </ol>
+ </li>
+ <li>Add the <a target="_blank" href="x86FSP1_1.html#FspBinary">FSP binary file</a> to the flash image</li>
+ <li>Set the following Kconfig values:
+ <ul>
+ <li>CONFIG_FSP_LOC to the FSP base address specified in the previous step</li>
+ <li>CONFIG_FSP_IMAGE_ID_STRING</li>
+ </ul>
+ </li>
+ <li>Debug the result until port 0x80 outputs
+ <ol type="A">
+ <li>0x90: <a target="_blank" href="https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2015.07/src/include/console/post_codes.h#209">POST_FSP_TEMP_RAM_INIT</a>
+ - Just before calling
+ <a target="_blank" href="https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2015.07/src/drivers/intel/fsp1_1/cache_as_ram.inc#90">TempRamInit</a>
+ </li>
+ <li>Alternating 0xbb and 0x02 - TempRamInit executed, no CPU microcode update found</li>
+ </ol>
+ </li>
+ <li>Add the CPU microcode update file
+ <ol type="A">
+ <li>Add the microcode file with the following command
+<pre><code>util/cbfstool/cbfstool build/coreboot.rom add -t microcode -n cpu_microcode_blob.bin -b <base address> -f cpu_microcode_blob.bin</code></pre>
+ </li>
+ <li>Set the Kconfig values
+ <ul>
+ <li>CONFIG_CPU_MICROCODE_CBFS_LOC set to the value from the previous step</li>
+ <li>CONFIG_CPU_MICROCODE_CBFS_LEN</li>
+ </ul>
+ </li>
+ </ol>
+ </li>
+ <li>Debug the result until port 0x80 outputs
+ <ol type="A">
+ <li>0x90: <a target="_blank" href="https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2015.07/src/include/console/post_codes.h#209">POST_FSP_TEMP_RAM_INIT</a>
+ - Just before calling
+ <a target="_blank" href="https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2015.07/src/drivers/intel/fsp1_1/cache_as_ram.inc#90">TempRamInit</a>
+ </li>
+ <li>0x23 - Just before calling
+ <a target="_blank" href="https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2015.07/src/drivers/intel/fsp1_1/cache_as_ram.inc#167">cache_as_ram_main</a>
+ which is the start of the verstage code which may be part of romstage
+ </li>
+ </ol>
+ </li>
+</ol>
+
+
+<hr>
<p>Modified: 24 January 2016</p>
</body>
</html>
\ No newline at end of file
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