[coreboot-gerrit] Patch set updated for coreboot: soc/apollolake: clear whole contents of cache-as-ram

[Alexandru Gagniuc (mr.nuke.me@gmail.com)]

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13312

-gerrit

commit 1de85a17552058016d2373b9dec877e1571fa132
Author: Andrey Petrov <andrey.petrov at intel.com>
Date:   Thu Oct 22 09:41:07 2015 -0700

    soc/apollolake: clear whole contents of cache-as-ram
    
    Some code makes assumption on memory to be cleared. In particular
    we must clear area occupied by car.data. FSP seems to be also
    making assumption stack memory is zeroed. This can be further
    reworked to clear only areas that have to be cleared for the sake
    of saving cycles.
    
    Change-Id: I9d75cb0a15f2bebf47d53daf7e4d76865a4c166b
    Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
 src/soc/intel/apollolake/bootblock/cache_as_ram.S | 12 ++++--------
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram.S b/src/soc/intel/apollolake/bootblock/cache_as_ram.S
index e451f66..5bbf6cc 100644
--- a/src/soc/intel/apollolake/bootblock/cache_as_ram.S
+++ b/src/soc/intel/apollolake/bootblock/cache_as_ram.S
@@ -104,15 +104,11 @@ clear_var_mtrr:
 
 	post_code(0x26)
 
-	/* Write something to each cache line */
-	mov	eax, 0xcafebabe
+	/* Clear the cache memory region. This will also fill up the cache */
 	mov	edi, CONFIG_DCACHE_RAM_BASE
-	mov	ecx, (0x80000 >> 6)
-cache_init_loop:
-	mov	[edi], eax
-	sfence
-	add	edi, 64
-	loop cache_init_loop
+	mov	ecx, CONFIG_DCACHE_RAM_SIZE >> 2
+	xor	eax, eax
+	rep	stos dword ptr es:[edi], eax
 
 	post_code(0x27)