[coreboot-gerrit] Patch set updated for coreboot: soc/apollolake: Add support for memory-mapped boot media

[Alexandru Gagniuc (mr.nuke.me@gmail.com)]

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13309

-gerrit

commit 03fb1f086ca045fc8b1a3ed4245b166ccc23bd2f
Author: Andrey Petrov <andrey.petrov at intel.com>
Date:   Wed Oct 14 11:16:30 2015 -0700

    soc/apollolake: Add support for memory-mapped boot media
    
    On Apollo Lake SPI flash is memory mapped. The mapping is
    different to previous platforms. Only "BIOS" region is mapped
    in contrast to whole flash.
    
    Change-Id: Ib57e01310c1a2b91e027abcbd6ac2c5cad9fddf3
    Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
 src/soc/intel/apollolake/Kconfig      | 18 ++++++++++
 src/soc/intel/apollolake/Makefile.inc |  3 ++
 src/soc/intel/apollolake/mmap_boot.c  | 63 +++++++++++++++++++++++++++++++++++
 3 files changed, 84 insertions(+)

diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index e5b0649..4a4efa4 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -36,6 +36,10 @@ config CPU_SPECIFIC_OPTIONS
 	select UDELAY_TSC
 	select TSC_CONSTANT_RATE
 
+config X86_TOP4G_BOOTMEDIA_MAP
+	bool
+	default n
+
 config MMCONF_BASE_ADDRESS
 	hex "PCI MMIO Base Address"
 	default 0xe0000000
@@ -67,6 +71,20 @@ config DCACHE_RAM_BOOTBLOCK_STACK_SIZE
 	  The amount of anticipated stack usage from the bootblock during
 	  pre-romstage initialization.
 
+config IFD_BIOS_START
+	hex
+	default 0x1000
+	help
+	  The starting address of flash region 1 (BIOS), as declared in the
+	  firmware descriptor. This can be obtained via 'ifdtool -d'.
+
+config IFD_BIOS_SIZE
+	hex
+	default ROM_SIZE
+	help
+	  The ending address of flash region 1 (BIOS), as declared in the
+	  firmware descriptor. This can be obtained via 'ifdtool -d'.
+
 config CPU_ADDR_BITS
 	int
 	default 36
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 9d3897f..4b0b31d 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -12,14 +12,17 @@ bootblock-y += cpu.c
 bootblock-y += gpio.c
 bootblock-y += bootblock/cache_as_ram.S
 bootblock-y += bootblock/early_chipset_config.S
+bootblock-y += mmap_boot.c
 bootblock-y += uart_early.c
 
 romstage-y += cpu.c
 romstage-y += gpio.c
+romstage-y += mmap_boot.c
 romstage-y += uart_early.c
 
 ramstage-y += cpu.c
 ramstage-y += gpio.c
+ramstage-y += mmap_boot.c
 ramstage-y += uart.c
 
 romstage-y += placeholders.c
diff --git a/src/soc/intel/apollolake/mmap_boot.c b/src/soc/intel/apollolake/mmap_boot.c
new file mode 100644
index 0000000..7e9080b
--- /dev/null
+++ b/src/soc/intel/apollolake/mmap_boot.c
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Andrey Petrov <andrey.petrov at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <boot_device.h>
+#include <console/console.h>
+#include <cbfs.h>
+#include <endian.h>
+#include <stdlib.h>
+#include <commonlib/region.h>
+#include <fmap.h>
+
+/*
+ *  If Apollo Lake is configured to boot from SPI flash "BIOS" region
+ *  (as defined in descriptor) is mapped below 4GiB.  Form a pointer for
+ *  the base.
+ */
+#define ROM_BASE ((void *)(uintptr_t)(0x100000000ULL - CONFIG_IFD_BIOS_SIZE))
+
+static const struct mem_region_device boot_dev = {
+	.base = (void *) ROM_BASE,
+	/* typically not whole flash is memory mapped */
+	.rdev = REGION_DEV_INIT(&mem_rdev_ops, CONFIG_IFD_BIOS_START,
+							CONFIG_IFD_BIOS_SIZE)
+};
+
+const struct region_device *boot_device_ro(void)
+{
+	return &boot_dev.rdev;
+}
+
+static int iafw_boot_region_properties(struct cbfs_props *props)
+{
+	struct region regn;
+
+	/* use fmap to locate CBFS area */
+	if (fmap_locate_area("COREBOOT", &regn))
+		return 1;
+
+	props->offset = regn.offset;
+	props->size = regn.size;
+
+	printk(BIOS_DEBUG, "CBFS @ %zx size %zx\n", props->offset, props->size);
+
+	return 0;
+}
+
+/*
+ * Named cbfs_master_header_locator so that it overrides the default, but
+ * incompatible locator in cbfs.c
+ */
+const struct cbfs_locator cbfs_master_header_locator = {
+	.name = "IAFW Locator",
+	.locate = iafw_boot_region_properties,
+};