[coreboot-gerrit] Patch set updated for coreboot: soc/apollolake: Disable watchdog timer after console initialization

[Alexandru Gagniuc (mr.nuke.me@gmail.com)]

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13311

-gerrit

commit 1eff21041805fc146aa59fff95c850906d250027
Author: Alexandru Gagniuc <alexandrux.gagniuc at intel.com>
Date:   Fri Oct 9 17:34:46 2015 -0700

    soc/apollolake: Disable watchdog timer after console initialization
    
    Change-Id: I0680d3866cece70e3ea03b5c1b22769149fc2278
    Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc at intel.com>
---
 src/soc/intel/apollolake/bootblock/bootblock_car.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/src/soc/intel/apollolake/bootblock/bootblock_car.c b/src/soc/intel/apollolake/bootblock/bootblock_car.c
index 3a0110e..e9cbb09 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock_car.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock_car.c
@@ -12,9 +12,26 @@
 
 #include <arch/io.h>
 #include <console/console.h>
+#include <device/pci.h>
 #include <soc/bootblock.h>
 #include <soc/uart.h>
 
+static void disable_watchdog(void)
+{
+	uint32_t reg;
+	device_t dev = PCI_DEV(0, 0xd, 1);
+
+	/* Open up an IO window */
+	pci_write_config16(dev, PCI_BASE_ADDRESS_4, 0x400);
+	pci_write_config32(dev, PCI_COMMAND,
+			   PCI_COMMAND_MASTER | PCI_COMMAND_IO);
+
+	/* We don't have documentation for this bit, but it prevents reboots */
+	reg = inl(0x400 + 0x68);
+	reg |= 1 << 11;
+	outl(reg, 0x400 + 0x68);
+}
+
 void bootblock_car_main(void)
 {
 	/* Quick post code to show we made it to C code */
@@ -25,6 +42,9 @@ void bootblock_car_main(void)
 		console_init();
 	}
 
+	/* Wait until after we have console to disable this */
+	disable_watchdog();
+
 	/* Don't return, so we see the above post code */
 	while (1)
 		;