[coreboot-gerrit] Patch set updated for coreboot: soc/apollolake: Add UART and debug console support
Alexandru Gagniuc (mr.nuke.me@gmail.com)
gerrit at coreboot.org
Mon Jan 25 21:30:59 CET 2016
Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13308
-gerrit
commit 3c67359072b0250b398a1cbbf1236e71b79c72b3
Author: Alexandru Gagniuc <alexandrux.gagniuc at intel.com>
Date: Wed Oct 7 12:59:31 2015 -0700
soc/apollolake: Add UART and debug console support
The UART uses a standard 8250 32-bit register map, and some config
registers in the same memory window. Set it up for console.
Change-Id: I866ff67d121826594b634cd00b6ef693b1d64512
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc at intel.com>
---
src/soc/intel/apollolake/Kconfig | 6 ++
src/soc/intel/apollolake/Makefile.inc | 3 +
src/soc/intel/apollolake/bootblock/bootblock_car.c | 8 +++
src/soc/intel/apollolake/include/soc/uart.h | 28 ++++++++
src/soc/intel/apollolake/uart.c | 22 ++++++
src/soc/intel/apollolake/uart_early.c | 78 ++++++++++++++++++++++
6 files changed, 145 insertions(+)
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 825a40f..3267737 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -20,6 +20,7 @@ config CPU_SPECIFIC_OPTIONS
# Misc options
select C_ENVIRONMENT_BOOTBLOCK
select COLLECT_TIMESTAMPS
+ select DRIVERS_UART_8250MEM_32
select HAVE_INTEL_FIRMWARE
select MMCONF_SUPPORT
select MMCONF_SUPPORT_DEFAULT
@@ -42,6 +43,11 @@ config IOSF_BASE_ADDRESS
hex "MMIO Base Address of sideband bus"
default 0xd0000000
+config CONSOLE_UART_BASE_ADDRESS
+ depends on CONSOLE_SERIAL
+ hex "MMIO base address for UART"
+ default 0xde000000
+
config DCACHE_RAM_BASE
hex "Base address of cache-as-RAM"
default 0xfef00000
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 9d33fe5..9d3897f 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -12,12 +12,15 @@ bootblock-y += cpu.c
bootblock-y += gpio.c
bootblock-y += bootblock/cache_as_ram.S
bootblock-y += bootblock/early_chipset_config.S
+bootblock-y += uart_early.c
romstage-y += cpu.c
romstage-y += gpio.c
+romstage-y += uart_early.c
ramstage-y += cpu.c
ramstage-y += gpio.c
+ramstage-y += uart.c
romstage-y += placeholders.c
smm-y += placeholders.c
diff --git a/src/soc/intel/apollolake/bootblock/bootblock_car.c b/src/soc/intel/apollolake/bootblock/bootblock_car.c
index 4be0815..3a0110e 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock_car.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock_car.c
@@ -11,12 +11,20 @@
*/
#include <arch/io.h>
+#include <console/console.h>
#include <soc/bootblock.h>
+#include <soc/uart.h>
void bootblock_car_main(void)
{
/* Quick post code to show we made it to C code */
outb(0x30, 0x80);
+
+ if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) {
+ lpss_console_uart_init();
+ console_init();
+ }
+
/* Don't return, so we see the above post code */
while (1)
;
diff --git a/src/soc/intel/apollolake/include/soc/uart.h b/src/soc/intel/apollolake/include/soc/uart.h
new file mode 100644
index 0000000..fd535fb
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/uart.h
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _SOC_APOLLOLAKE_UART_H_
+#define _SOC_APOLLOLAKE_UART_H_
+
+/* Clock is 100MHz * (M / N).*/
+#define UART_CLK 0x200
+# define UART_CLK_UPDATE (1 << 31)
+# define UART_CLK_DIV_N(n) (((n) & 0x7fff) << 16)
+# define UART_CLK_DIV_M(m) (((m) & 0x7fff) << 1)
+# define UART_CLK_EN (1 << 0)
+#define UART_RESET 0x204
+# define UART_RESET_DMA_EN (1 << 2)
+# define UART_RESET_UART_EN (3 << 0)
+
+void lpss_console_uart_init(void);
+
+#endif /* _SOC_APOLLOLAKE_UART_H_ */
diff --git a/src/soc/intel/apollolake/uart.c b/src/soc/intel/apollolake/uart.c
new file mode 100644
index 0000000..9663130
--- /dev/null
+++ b/src/soc/intel/apollolake/uart.c
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <console/uart.h>
+
+/*
+ * TODO: We need a mechanism to return the new BAR once the resource allocator
+ * gives us a new location.
+ */
+uintptr_t uart_platform_base(int idx)
+{
+ return (CONFIG_CONSOLE_UART_BASE_ADDRESS);
+}
diff --git a/src/soc/intel/apollolake/uart_early.c b/src/soc/intel/apollolake/uart_early.c
new file mode 100644
index 0000000..bc02776
--- /dev/null
+++ b/src/soc/intel/apollolake/uart_early.c
@@ -0,0 +1,78 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <console/uart.h>
+#include <device/pci.h>
+#include <soc/gpio.h>
+#include <soc/uart.h>
+
+static const struct pad_config uart_tx_pad_configs[] = {
+ {
+ .community = GPIO_NORTH,
+ .pad = 39,
+ .config = {PAD_CFG0_DEFAULT_FUNC(1), PAD_CFG1_DEFAULT_NATIVE},
+ }, {
+ .community = GPIO_NORTH,
+ .pad = 42,
+ .config = {PAD_CFG0_DEFAULT_FUNC(1), PAD_CFG1_DEFAULT_NATIVE},
+ }, {
+ .community = GPIO_NORTH,
+ .pad = 47,
+ .config = {PAD_CFG0_DEFAULT_FUNC(1), PAD_CFG1_DEFAULT_NATIVE},
+ },
+};
+
+static void lpss_uart_write(uint16_t reg, uint32_t val)
+{
+ uintptr_t base = CONFIG_CONSOLE_UART_BASE_ADDRESS | reg;
+ write32((void *)base, val);
+}
+
+void lpss_console_uart_init(void)
+{
+ uint32_t clk_sel;
+ device_t uart = PCI_DEV(0, 0x18, CONFIG_UART_FOR_CONSOLE & 3);
+
+ if(CONFIG_UART_FOR_CONSOLE > 2)
+ return;
+
+ gpio_configure_pad(&uart_tx_pad_configs[CONFIG_UART_FOR_CONSOLE]);
+
+ /* Enable BAR0 for the UART -- this is where the 8250 registers hide */
+ pci_write_config32(uart, PCI_BASE_ADDRESS_0,
+ CONFIG_CONSOLE_UART_BASE_ADDRESS);
+
+ /* Enable memory access and bus master */
+ pci_write_config32(uart, PCI_COMMAND,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+
+ /* Take UART out of reset */
+ lpss_uart_write(UART_RESET, UART_RESET_DMA_EN | UART_RESET_UART_EN);
+
+ /* These values get us a 1.836 MHz clock (ideally we want 1.843 MHz) */
+ clk_sel = UART_CLK_DIV_N(0x7fff) | UART_CLK_DIV_M(0x025a);
+ /* Set M and N divisor inputs and enable clock */
+ lpss_uart_write(UART_CLK, clk_sel | UART_CLK_UPDATE);
+ lpss_uart_write(UART_CLK, clk_sel | UART_CLK_EN);
+
+}
+
+uintptr_t uart_platform_base(int idx)
+{
+ return (CONFIG_CONSOLE_UART_BASE_ADDRESS);
+}
+
+unsigned int uart_platform_refclk(void)
+{
+ /* That's within 0.5% of the actual value we've set earlier */
+ return 115200 * 16;
+}
More information about the coreboot-gerrit
mailing list