[coreboot-gerrit] Patch set updated for coreboot: soc/apollolake: Add workaround for silicon cache BUG

[Alexandru Gagniuc (mr.nuke.me@gmail.com)]

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13321

-gerrit

commit c65ac75a6be6b868da499d162f28b366da81e25a
Author: Alexandru Gagniuc <alexandrux.gagniuc at intel.com>
Date:   Tue Oct 27 16:38:25 2015 -0700

    soc/apollolake: Add workaround for silicon cache BUG
    
    When updating a cache line, it becomes non-executable. This workaround
    allow re-marking all the cache as executable after an update.
    
    Change-Id: Idd3cc1db9cca432b9d1382950e8bc087279e1fbb
    Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc at intel.com>
---
 src/soc/intel/apollolake/include/soc/cpu.h | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h
index d0d6afd..9c32e8e 100644
--- a/src/soc/intel/apollolake/include/soc/cpu.h
+++ b/src/soc/intel/apollolake/include/soc/cpu.h
@@ -13,8 +13,21 @@
 #ifndef _SOC_APOLLOLAKE_CPU_H_
 #define _SOC_APOLLOLAKE_CPU_H_
 
+#include <cpu/x86/msr.h>
+
 #define MSR_PLATFORM_INFO	0xce
 
 #define BASE_CLOCK_MHZ		100
 
+/*
+ * Remark the cache as executable. This works around a silicon bug where
+ * updating a cache line makes it non-executable.
+ */
+static inline void bxt_remark_cache_exec(void)
+{
+	msr_t msr = rdmsr(0x120);
+	msr.lo |= (1 << 8);
+	wrmsr(0x120, msr);
+}
+
 #endif /* _SOC_APOLLOLAKE_CPU_H_ */