[coreboot-gerrit] Patch set updated for coreboot: soc/apollolake: Add memory and reserve MMIO resources
Alexandru Gagniuc (mr.nuke.me@gmail.com)
gerrit at coreboot.org
Mon Jan 25 18:02:37 CET 2016
Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13360
-gerrit
commit 1f6700abe3e5a031ced1cffc37ed866eec6d3504
Author: Andrey Petrov <andrey.petrov at intel.com>
Date: Tue Nov 10 13:52:29 2015 -0800
soc/apollolake: Add memory and reserve MMIO resources
This adds most important MMIO reserved memory resources,
real DRAM memory resources, and some DRAM resources that
can not be used as RAM for whatever reason.
Change-Id: Id5a80cf18d67ace991e8046fa46c4b7ed47c626a
Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
src/soc/intel/apollolake/Makefile.inc | 1 +
src/soc/intel/apollolake/include/soc/iomap.h | 1 +
src/soc/intel/apollolake/include/soc/northbridge.h | 30 +++++
src/soc/intel/apollolake/northbridge.c | 141 +++++++++++++++++++++
4 files changed, 173 insertions(+)
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index e9f1079..23a2151 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -30,6 +30,7 @@ ramstage-y += gpio.c
ramstage-y += lpc.c
ramstage-y += memmap.c
ramstage-y += mmap_boot.c
+ramstage-y += northbridge.c
ramstage-y += tsc_freq.c
ramstage-y += uart.c
diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h
index 09ae67d..d12eb19 100644
--- a/src/soc/intel/apollolake/include/soc/iomap.h
+++ b/src/soc/intel/apollolake/include/soc/iomap.h
@@ -15,6 +15,7 @@
#define P2SB_BAR 0xd0000000
#define MCH_BASE_ADDR 0xfed10000
+#define MCH_BASE_SIZE (32 * KiB)
#define ACPI_PMIO_BASE 0x400
#define R_ACPI_PM1_TMR 0x8
diff --git a/src/soc/intel/apollolake/include/soc/northbridge.h b/src/soc/intel/apollolake/include/soc/northbridge.h
new file mode 100644
index 0000000..583e117
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/northbridge.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Andrey Petrov <andrey.petrov at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _SOC_APOLLOLAKE_NORTHBRIDGE_H_
+#define _SOC_APOLLOLAKE_NORTHBRIDGE_H_
+
+#include <soc/iomap.h>
+
+#define MCHBAR 0x48
+#define PCIEXBAR 0x60
+#define PCIEX_SIZE (256 * MiB)
+
+#define BDSM 0xb0 /* Base Data Stolen Memory */
+#define BGSM 0xb4 /* Base GTT Stolen Memory */
+#define TSEG 0xb8 /* TSEG base */
+#define TOLUD 0xbc /* Top of Low Used Memory */
+#define TOUUD 0xa8 /* Top of Upper Usable DRAM */
+
+#define MCH_APOLLOLAKE_ID 0x5af0
+
+#endif /* _SOC_APOLLOLAKE_NORTHBRIDGE_H_ */
diff --git a/src/soc/intel/apollolake/northbridge.c b/src/soc/intel/apollolake/northbridge.c
new file mode 100644
index 0000000..fefc947
--- /dev/null
+++ b/src/soc/intel/apollolake/northbridge.c
@@ -0,0 +1,141 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Andrey Petrov <andrey.petrov at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <console/console.h>
+#include <soc/iomap.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <soc/northbridge.h>
+
+static uint32_t get_bar(device_t dev, unsigned int index)
+{
+ uint32_t bar;
+
+ bar = pci_read_config32(dev, index);
+
+ /* If not enabled return 0 else strip enabled bit */
+ return (bar & 1) ? (bar & ~1) : 0;
+}
+
+static int mc_add_fixed_mmio_resources(device_t dev, int index)
+{
+ struct resource *res;
+
+ /* PCI extended config region */
+ res = new_resource(dev, index++);
+ res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
+ IORESOURCE_RESERVE | IORESOURCE_ASSIGNED;
+ /* only last 4 bits encode BAR */
+ res->base = get_bar(dev, PCIEXBAR) & 0xf0000000;
+ res->size = PCIEX_SIZE;
+
+ /* Memory Controller HUB */
+ res = new_resource(dev, index++);
+ res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
+ IORESOURCE_RESERVE | IORESOURCE_ASSIGNED;
+ /* BITS 31:15 encode BAR */
+ res->base = get_bar(dev, MCHBAR) & 0xffff8000;
+ res->size = MCH_BASE_SIZE;
+ return index;
+}
+
+
+static int mc_add_dram_resources(device_t dev, int index)
+{
+ unsigned long base_k, size_k;
+ struct resource *resource;
+
+ struct reserved_ram {
+ uint32_t bgsm;
+ uint32_t bdsm;
+ uint32_t tolud;
+ uint32_t tseg;
+ } aplk_reserved_ram;
+
+ aplk_reserved_ram.bgsm = pci_read_config32(dev, BGSM);
+ aplk_reserved_ram.bdsm = pci_read_config32(dev, BDSM);
+ aplk_reserved_ram.tolud = pci_read_config32(dev, TOLUD);
+ aplk_reserved_ram.tseg = pci_read_config32(dev, TSEG);
+
+ /* 0 - > 0xa0000: 640kb of DOS memory. Not enough for anybody nowadays */
+ ram_resource(dev, index++, 0, 640);
+
+ /* 0xc0000 -> top_of_ram, skipping the legacy VGA region */
+ base_k = 768;
+ size_k = (aplk_reserved_ram.tseg >> 10) - base_k;
+ ram_resource(dev, index++, base_k, size_k);
+
+ /* TSEG -> BGSM */
+ resource = new_resource(dev, index++);
+ resource->base = aplk_reserved_ram.tseg;
+ resource->size = aplk_reserved_ram.bgsm - resource->base;
+ resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
+ IORESOURCE_STORED | IORESOURCE_RESERVE |
+ IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE;
+
+ /* BGSM -> BDSM */
+ resource = new_resource(dev, index++);
+ resource->base = aplk_reserved_ram.bgsm;
+ resource->size = aplk_reserved_ram.bdsm - resource->base;
+ resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
+ IORESOURCE_STORED | IORESOURCE_RESERVE |
+ IORESOURCE_ASSIGNED;
+
+ /* BDSM -> TOLUD */
+ resource = new_resource(dev, index++);
+ resource->base = aplk_reserved_ram.bdsm;
+ resource->size = aplk_reserved_ram.tolud - resource->base;
+ resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
+ IORESOURCE_STORED | IORESOURCE_RESERVE |
+ IORESOURCE_ASSIGNED;
+
+ /* 0xa0000 - 0xbffff: legacy VGA */
+ mmio_resource(dev, index++, 640, 128);
+
+ /* 0xe0000 - 0xfffff: PAM area */
+ reserved_ram_resource(dev, index++, 768, 256);
+
+ return index;
+}
+
+static void northbridge_read_resources(device_t dev)
+{
+
+ int index = 0;
+ /* Read standard PCI resources. */
+ pci_dev_read_resources(dev);
+
+ /* Add all fixed MMIO resources. */
+ index = mc_add_fixed_mmio_resources(dev, index);
+
+ /* Calculate and add DRAM resources. */
+ mc_add_dram_resources(dev, index);
+}
+
+static struct device_operations northbridge_ops = {
+ .read_resources = northbridge_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = DEVICE_NOOP,
+ .enable = DEVICE_NOOP
+};
+
+static const unsigned short northbridge_ids[] = {
+ MCH_APOLLOLAKE_ID,
+ 0
+};
+
+static const struct pci_driver northbridge_driver __pci_driver = {
+ .ops = &northbridge_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .devices = northbridge_ids
+};
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