[coreboot-gerrit] Patch merged into coreboot/master: nb/amd/mct_ddr3: Properly set MR0 WR value

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit db84a99011bef90c57fcbbd168c95ca6d7aceafd
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date:   Tue Nov 24 14:11:52 2015 -0600

    nb/amd/mct_ddr3: Properly set MR0 WR value
    
    The existing code accidentally truncated the MSB from the MR0
    WR value.  While this probably had a minimal effect in reality,
    it should be configured correctly for maximal system stability.
    
    Change-Id: Ifb8a39c6ca47b32b44d33735e5c6c39f1dc5a44e
    Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
    Reviewed-on: https://review.coreboot.org/13147
    Tested-by: build bot (Jenkins)
    Tested-by: Raptor Engineering Automated Test Stand <noreply at raptorengineeringinc.com>
    Reviewed-by: Felix Held <felix-coreboot at felixheld.de>
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>


See https://review.coreboot.org/13147 for details.

-gerrit