[coreboot-gerrit] New patch to review for coreboot: soc/appollolake: Write correct framebuffer base in lb_framebuffer

Andrey Petrov (andrey.petrov@intel.com) gerrit at coreboot.org
Sun Jan 24 03:34:06 CET 2016


Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13393

-gerrit

commit 554fa51a5469e38c857c1ebab876e4f10e1c9d25
Author: Alexandru Gagniuc <alexandrux.gagniuc at intel.com>
Date:   Wed Dec 23 11:25:27 2015 -0800

    soc/appollolake: Write correct framebuffer base in lb_framebuffer
    
    FSP returns a base address for the framebuffer, but that base address
    is actually a PCI BAR, which is moved during resource allocation.
    Instead of writing the FSP provided value to the lb_framebuffer, write
    the address the resource allocator has selected.
    
    Change-Id: I0c6bf4d65940aa2d64fbf7e7593bc339162faffe
    Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc at intel.com>
---
 src/soc/intel/apollolake/graphics.c | 40 ++++++++++++++++++++++++++++++++++++-
 1 file changed, 39 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/apollolake/graphics.c b/src/soc/intel/apollolake/graphics.c
index 7b9a75c..7186a28 100644
--- a/src/soc/intel/apollolake/graphics.c
+++ b/src/soc/intel/apollolake/graphics.c
@@ -12,6 +12,12 @@
 
 #include <console/console.h>
 #include <fsp/util.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <soc/pci_ids.h>
+
+static uintptr_t framebuffer_bar = (uintptr_t)NULL;
 
 void lb_framebuffer(struct lb_header *header)
 {
@@ -20,6 +26,38 @@ void lb_framebuffer(struct lb_header *header)
 
 	framebuffer = (void *)lb_new_record(header);
 	ret = fsp_fill_lb_framebuffer(framebuffer);
-	if (ret != CB_SUCCESS)
+	if (ret != CB_SUCCESS) {
 		printk(BIOS_ALERT, "FSP did not return a valid framebuffer\n");
+		return;
+        }
+
+	/* Resource allocator can move the BAR around after FSP configures it */
+	if (!framebuffer_bar) {
+		printk(BIOS_ALERT, "Framebuffer BAR invalid (00:02.0 BAR2)\n");
+		return;
+	}
+
+	framebuffer->physical_address = framebuffer_bar;
+	printk(BIOS_DEBUG, "Graphics framebuffer located at 0x%llx\n",
+	       framebuffer->physical_address);
+}
+
+static void igd_set_resources(struct device *dev)
+{
+	framebuffer_bar = find_resource(dev, PCI_BASE_ADDRESS_2)->base;
+	pci_dev_set_resources(dev);
 }
+
+static struct device_operations igd_ops = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = igd_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = pci_dev_init,
+	.enable           = DEVICE_NOOP
+};
+
+static const struct pci_driver uart_driver __pci_driver = {
+	.ops	= &igd_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEV_ID_APOLLOLAKE_IGD,
+};



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