[coreboot-gerrit] New patch to review for coreboot: nb/amd/mct_ddr3: Properly set MR0 WR value

[Timothy Pearson (tpearson@raptorengineeringinc.com)]

Timothy Pearson (tpearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13147

-gerrit

commit 1d18c9a35f29e827274d6fa05a0f7b31c1bf3ef8
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date:   Tue Nov 24 14:11:52 2015 -0600

    nb/amd/mct_ddr3: Properly set MR0 WR value
    
    The existing code accidentally truncated the MSB from the MR0
    WR value.  While this probably had a minimal effect in reality,
    it should be configured correctly for maximal system stability.
    
    Change-Id: Ifb8a39c6ca47b32b44d33735e5c6c39f1dc5a44e
    Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
---
 src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c
index 822d813..bcf6031 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c
@@ -967,7 +967,7 @@ static u32 mct_MR0(struct MCTStatStruc *pMCTstat,
 
 		/* Load data into MRS word */
 		ret |= (ppd & 0x1) << 12;
-		ret |= (wr_ap & 0x3) << 9;
+		ret |= (wr_ap & 0x7) << 9;
 		ret |= (dll_reset & 0x1) << 8;
 		ret |= (test_mode & 0x1) << 7;
 		ret |= ((cas_latency & 0xe) >> 1) << 4;