[coreboot-gerrit] Patch set updated for coreboot: nb/intel/x4x: Cleanup gma.c

[Damien Zammit (damien@zamaudio.com)]

Damien Zammit (damien at zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13128

-gerrit

commit ff797c5c1537297a44f3a9ad8cc415fe4e8b631a
Author: Damien Zammit <damien at zamaudio.com>
Date:   Fri Jan 22 19:13:18 2016 +1100

    nb/intel/x4x: Cleanup gma.c
    
    Tidy up the code and move vga_textmode_init() later
    
    Change-Id: I49967e7197416c955ae6c8775eac7d1a60c92d1c
    Signed-off-by: Damien Zammit <damien at zamaudio.com>
---
 src/northbridge/intel/x4x/gma.c | 30 +++++++++++-------------------
 1 file changed, 11 insertions(+), 19 deletions(-)

diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c
index 7891229..f346044 100644
--- a/src/northbridge/intel/x4x/gma.c
+++ b/src/northbridge/intel/x4x/gma.c
@@ -43,19 +43,13 @@ void gtt_write(u32 reg, u32 data)
 }
 
 static void intel_gma_init(const struct northbridge_intel_x4x_config *info,
-			   u8 *mmio, u32 physbase, u16 piobase, u32 lfb)
+			   u8 *mmio, u32 physbase, u16 piobase)
 {
 
 	int i;
 	u32 hactive, vactive;
-	vga_gr_write(0x18, 0);
 
-	/* Setup GTT.  */
-	for (i = 0; i < 0x2000; i++)
-	{
-		outl((i << 2) | 1, piobase);
-		outl(physbase + (i << 12) + 1, piobase + 4);
-	}
+	vga_gr_write(0x18, 0);
 
 	write32(mmio + VGA0, 0x31108);
 	write32(mmio + VGA1, 0x31406);
@@ -92,8 +86,6 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info,
 	hactive = 640;
 	vactive = 400;
 
-	vga_textmode_init();
-
 	mdelay(1);
 	write32(mmio + FP0(0), 0x31108);
 	write32(mmio + DPLL(0),
@@ -168,7 +160,7 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info,
 			| ADPA_DPMS_ON
 			);
 
-	write32(mmio + PP_CONTROL, PANEL_POWER_ON);
+	vga_textmode_init();
 
 	/* Enable screen memory.  */
 	vga_sr_write(1, vga_sr_read(1) & ~0x20);
@@ -197,24 +189,24 @@ static void gma_func0_init(struct device *dev)
 		pci_dev_init(dev);
 	} else {
 		u32 physbase;
-		struct resource *lfb_res;
 		struct resource *pio_res;
 
-		lfb_res = find_resource(dev, PCI_BASE_ADDRESS_2);
 		pio_res = find_resource(dev, PCI_BASE_ADDRESS_4);
 
 		physbase = pci_read_config32(dev, 0x5c) & ~0xf;
 
-		if (gtt_res && gtt_res->base && physbase && pio_res && pio_res->base
-		    && lfb_res && lfb_res->base) {
-			printk(BIOS_SPEW, "Initializing VGA without OPROM. MMIO 0x%llx\n",
-			       gtt_res->base);
+		if (gtt_res && gtt_res->base && physbase
+				&& pio_res && pio_res->base) {
+			printk(BIOS_SPEW,
+				"Initializing VGA without OPROM. MMIO 0x%llx\n",
+				gtt_res->base);
 			intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase,
-				       pio_res->base, lfb_res->base);
+				       pio_res->base);
 		}
 
 		/* Linux relies on VBT for panel info.  */
-		generate_fake_intel_oprom(&conf->gfx, dev, "$VBT EAGLELAKE      ");
+		generate_fake_intel_oprom(&conf->gfx, dev,
+			"$VBT EAGLELAKE      ");
 	}
 
 	/* Post VBIOS init */