[coreboot-gerrit] New patch to review for coreboot: intel/strago: Set POWER_SOURCE_CONFIG in devicetree.cb

[Hannah Williams (hannah.williams@intel.com)]

Hannah Williams (hannah.williams at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13117

-gerrit

commit 5d427b51290f00d42710a62a11ffd7f0a69e6e05
Author: Kane Chen <kane.chen at intel.com>
Date:   Mon Oct 26 15:11:53 2015 +0800

    intel/strago: Set POWER_SOURCE_CONFIG in devicetree.cb
    
    SVID config set to  SVID_PMIC_CONFIG
    
    BUG=none
    BRANCH=none
    TEST=build, boot to OS and check the register is set properly
    
    Change-Id: If63b8112d4da0347c3a2c4c6d82b12a1f618291c
    Signed-off-by: Kane Chen <kane.chen at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/308576
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/intel/strago/devicetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/intel/strago/devicetree.cb b/src/mainboard/intel/strago/devicetree.cb
index bcf92f1..788153a 100755
--- a/src/mainboard/intel/strago/devicetree.cb
+++ b/src/mainboard/intel/strago/devicetree.cb
@@ -34,7 +34,7 @@ chip soc/intel/braswell
 	register "PcdEnableI2C5" = "1"
 	register "PcdEnableI2C6" = "1"
 	register "PunitPwrConfigDisable" = "0"	# Enable SVID
-	register "ChvSvidConfig" = "SVID_CONFIG1"
+	register "ChvSvidConfig" = "SVID_PMIC_CONFIG"
 	register "PcdEmmcMode" = "PCH_ACPI_MODE"
 	register "PcdUsb3ClkSsc" = "1"
 	register "PcdDispClkSsc" = "1"