[coreboot-gerrit] Patch set updated for coreboot: google/oak: Initialize DRAM
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Thu Jan 21 12:17:29 CET 2016
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13106
-gerrit
commit 6bba37d3b23e44c986d7ed48dec9630603a1634b
Author: Peter Kao <peter.kao at mediatek.com>
Date: Fri Jul 31 17:11:14 2015 +0800
google/oak: Initialize DRAM
BUG=none
TEST=emerge-oak coreboot
BRANCH=none
Change-Id: I3ed8bad1bdc7d17e334e0136f92a51c8e7ba4e67
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: b614eeb1bba5660438c214e82225832809caca8e
Original-Change-Id: I0f7b0a426dae1548b34114a024c92befdf6002f6
Original-Signed-off-by: Peter Kao <peter.kao at mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292692
Original-Commit-Ready: Yidi Lin <yidi.lin at mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin at mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
---
src/mainboard/google/oak/Makefile.inc | 2 +-
src/mainboard/google/oak/romstage.c | 8 ++
src/mainboard/google/oak/sdram_configs.c | 53 ++++++++++
.../oak/sdram_inf/sdram-lpddr3-hynix-2GB.inc | 116 +++++++++++++++++++++
.../oak/sdram_inf/sdram-lpddr3-samsung-2GB.inc | 116 +++++++++++++++++++++
.../google/oak/sdram_inf/sdram-unused.inc | 3 +
6 files changed, 297 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/google/oak/Makefile.inc b/src/mainboard/google/oak/Makefile.inc
index c7f0401..f0bbb7b 100644
--- a/src/mainboard/google/oak/Makefile.inc
+++ b/src/mainboard/google/oak/Makefile.inc
@@ -22,7 +22,7 @@ verstage-y += chromeos.c
verstage-y += memlayout.ld
romstage-y += chromeos.c
-romstage-y += romstage.c
+romstage-y += romstage.c sdram_configs.c
romstage-y += memlayout.ld
romstage-y += boardid.c
diff --git a/src/mainboard/google/oak/romstage.c b/src/mainboard/google/oak/romstage.c
index a60a50d..d72693f 100644
--- a/src/mainboard/google/oak/romstage.c
+++ b/src/mainboard/google/oak/romstage.c
@@ -19,6 +19,7 @@
#include <arch/mmu.h>
#include <cbfs.h>
+#include <cbmem.h>
#include <console/console.h>
#include <delay.h>
#include <program_loading.h>
@@ -26,6 +27,7 @@
#include <symbols.h>
#include <timestamp.h>
+#include <soc/emi.h>
#include <soc/mmu_operations.h>
#include <soc/rtc.h>
@@ -39,7 +41,13 @@ void main(void)
rtc_boot();
+ /* init memory */
+ mt_mem_init(get_sdram_config());
+
mt8173_mmu_after_dram();
+ /* should be called after memory init */
+ cbmem_initialize_empty();
+
run_ramstage();
}
diff --git a/src/mainboard/google/oak/sdram_configs.c b/src/mainboard/google/oak/sdram_configs.c
new file mode 100644
index 0000000..d5dcfac
--- /dev/null
+++ b/src/mainboard/google/oak/sdram_configs.c
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <boardid.h>
+#include <console/console.h>
+#include <soc/emi.h>
+#include <stdlib.h>
+
+static const struct mt8173_sdram_params sdram_configs[] = {
+#include "sdram_inf/sdram-lpddr3-hynix-2GB.inc" /* ram_code = 0000 */
+#include "sdram_inf/sdram-lpddr3-samsung-2GB.inc" /* ram_code = 0001 */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 0010 */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 0011 */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 0100 */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 0101 */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 0110 */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 0111 */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 1000 */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 1001 */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 1011 */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 1101 */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 1110 */
+#include "sdram_inf/sdram-unused.inc" /* ram_code = 1111 */
+};
+
+const struct mt8173_sdram_params *get_sdram_config(void)
+{
+ u32 ramcode = ram_code();
+
+ if (ramcode >= ARRAY_SIZE(sdram_configs)
+ || sdram_configs[ramcode].type == TYPE_INVALID)
+ die("Invalid RAMCODE.");
+
+ return &sdram_configs[ramcode];
+}
diff --git a/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-hynix-2GB.inc b/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-hynix-2GB.inc
new file mode 100644
index 0000000..4e728e3
--- /dev/null
+++ b/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-hynix-2GB.inc
@@ -0,0 +1,116 @@
+{ /* 2GB (8Gb + 8Gb) for single rank dram setting */
+ {
+ .impedance_drvp = 0x9,
+ .impedance_drvn = 0xa,
+ .datlat_ucfirst = 19,
+
+ .ca_train = {
+ [CHANNEL_A] = { 7, 7, 5, 6, 2, 1, 0, 1, 0, 2},
+ [CHANNEL_B] = { 1, 2, 2, 0, 2, 3, 3, 3, 3, 3}
+ },
+
+ .ca_train_center = {
+ [CHANNEL_A] = 2,
+ [CHANNEL_B] = 0
+ },
+
+ .wr_level = {
+ [CHANNEL_A] = { 5, 6, 5, 6},
+ [CHANNEL_B] = { 6, 6, 6, 4}
+ },
+
+ .gating_win = {
+ [CHANNEL_A] = {
+ { 28, 56},
+ { 0, 0}
+ },
+ [CHANNEL_B] = {
+ { 28, 56},
+ { 0, 0}
+ }
+ },
+
+ .rx_dqs_dly = {
+ [CHANNEL_A] = 0x110e0b0b,
+ [CHANNEL_B] = 0x12100d0d
+ },
+
+ .rx_dq_dly = {
+ [CHANNEL_A] = {
+ 0x01040302,
+ 0x04010300,
+ 0x02040300,
+ 0x04030302,
+ 0x04070400,
+ 0x07070707,
+ 0x05070808,
+ 0x00010404
+ },
+ [CHANNEL_B] = {
+ 0x05060604,
+ 0x04010400,
+ 0x05070300,
+ 0x05030504,
+ 0x07090500,
+ 0x08090707,
+ 0x080a0a0a,
+ 0x02000604
+ }
+ },
+ },
+ {
+ .actim = 0xaafd478c,
+ .actim1 = 0x91001f59,
+ .actim05t = 0x000025e1,
+ .conf1 = 0x00048403,
+ .conf2 = 0x030000a9,
+ .ddr2ctl = 0x000063b1,
+ .gddr3ctl1 = 0x11000000,
+ .misctl0 = 0x21000000,
+ .pd_ctrl = 0xd1976442,
+ .rkcfg = 0x002156c0,
+ .test2_3 = 0xbfc70401,
+ .test2_4 = 0x2801110d
+ },
+ {
+ .cona = 0x20102017,
+ .conb = 0x17283544,
+ .conc = 0x0a1a0b1a,
+ .cond = 0x00000000,
+ .cone = 0xffff0848,
+ .conf = 0x08420000,
+ .cong = 0x2b2b2a38,
+ .conh = 0x00000000,
+ .conm_1 = 0x40000500,
+ .conm_2 = 0x400005ff,
+ .mdct_1 = 0x80030303,
+ .mdct_2 = 0x34220c3f,
+ .test0 = 0xcccccccc,
+ .test1 = 0xcccccccc,
+ .testb = 0x00060124,
+ .testc = 0x38470000,
+ .testd = 0x00000000,
+ .arba = 0x7f077a49,
+ .arbc = 0xa0a070dd,
+ .arbd = 0x07007046,
+ .arbe = 0x40407046,
+ .arbf = 0xa0a070c6,
+ .arbg = 0xffff7047,
+ .arbi = 0x20406188,
+ .arbj = 0x9719595e,
+ .arbk = 0x64f3fc79,
+ .slct_1 = 0x00010800,
+ .slct_2 = 0xff03ff00,
+ .bmen = 0x00ff0001
+ },
+ {
+ .mrs_1 = 0x00830001,
+ .mrs_2 = 0x001c0002,
+ .mrs_3 = 0x00010003,
+ .mrs_10 = 0x00ff000a,
+ .mrs_11 = 0x0000000b,
+ .mrs_63 = 0x0000003f
+ },
+ .type = TYPE_LPDDR3,
+ .dram_freq = 896 * MHz,
+},
diff --git a/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-samsung-2GB.inc b/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-samsung-2GB.inc
new file mode 100644
index 0000000..4c58286
--- /dev/null
+++ b/src/mainboard/google/oak/sdram_inf/sdram-lpddr3-samsung-2GB.inc
@@ -0,0 +1,116 @@
+{ /* 2GB (8Gb + 8Gb) for dual rank dram setting */
+ {
+ .impedance_drvp = 0x9,
+ .impedance_drvn = 0xa,
+ .datlat_ucfirst = 18,
+
+ .ca_train = {
+ [CHANNEL_A] = { 6, 4, 3, 5, 4, 0, 0, 0, 0, 0},
+ [CHANNEL_B] = { 1, 1, 1, 1, 0, 6, 5, 5, 5, 7}
+ },
+
+ .ca_train_center = {
+ [CHANNEL_A] = 3,
+ [CHANNEL_B] = 3
+ },
+
+ .wr_level = {
+ [CHANNEL_A] = { 8, 10, 6, 8},
+ [CHANNEL_B] = { 9, 9, 7, 6}
+ },
+
+ .gating_win = {
+ [CHANNEL_A] = {
+ { 27, 64},
+ { 27, 72}
+ },
+ [CHANNEL_B] = {
+ { 27, 72},
+ { 27, 72}
+ }
+ },
+
+ .rx_dqs_dly = {
+ [CHANNEL_A] = 0x08080908,
+ [CHANNEL_B] = 0x0b0b060b
+ },
+
+ .rx_dq_dly = {
+ [CHANNEL_A] = {
+ 0x01010300,
+ 0x06030002,
+ 0x01010201,
+ 0x03020002,
+ 0x00010103,
+ 0x02010201,
+ 0x02040200,
+ 0x02020201
+ },
+ [CHANNEL_B] = {
+ 0x00020202,
+ 0x02020202,
+ 0x01020201,
+ 0x01010100,
+ 0x01010101,
+ 0x01000002,
+ 0x02000201,
+ 0x00010101,
+ }
+ },
+ },
+ {
+ .actim = 0xaafd478c,
+ .actim1 = 0x91001f59,
+ .actim05t = 0x000025e1,
+ .conf1 = 0x00048403,
+ .conf2 = 0x030000a9,
+ .ddr2ctl = 0x000063b1,
+ .gddr3ctl1 = 0x11000000,
+ .misctl0 = 0x21000000,
+ .pd_ctrl = 0xd1976442,
+ .rkcfg = 0x002156c1,
+ .test2_3 = 0xbfc70401,
+ .test2_4 = 0x2801110d
+ },
+ {
+ .cona = 0x50535057,
+ .conb = 0x17283544,
+ .conc = 0x0a1a0b1a,
+ .cond = 0x00000000,
+ .cone = 0xffff0848,
+ .conf = 0x08420000,
+ .cong = 0x2b2b2a38,
+ .conh = 0x00000000,
+ .conm_1 = 0x40000500,
+ .conm_2 = 0x400005ff,
+ .mdct_1 = 0x80030303,
+ .mdct_2 = 0x34220c3f,
+ .test0 = 0xcccccccc,
+ .test1 = 0xcccccccc,
+ .testb = 0x00060124,
+ .testc = 0x38470000,
+ .testd = 0x00000000,
+ .arba = 0x7f077a49,
+ .arbc = 0xa0a070dd,
+ .arbd = 0x07007046,
+ .arbe = 0x40407046,
+ .arbf = 0xa0a070c6,
+ .arbg = 0xffff7047,
+ .arbi = 0x20406188,
+ .arbj = 0x9719595e,
+ .arbk = 0x64f3fc79,
+ .slct_1 = 0x00010800,
+ .slct_2 = 0xff03ff00,
+ .bmen = 0x00ff0001
+ },
+ {
+ .mrs_1 = 0x00830001,
+ .mrs_2 = 0x001c0002,
+ .mrs_3 = 0x00010003,
+ .mrs_10 = 0x00ff000a,
+ .mrs_11 = 0x0000000b,
+ .mrs_63 = 0x0000003f
+ },
+ .type = TYPE_LPDDR3,
+ .dram_freq = 896 * MHz,
+},
diff --git a/src/mainboard/google/oak/sdram_inf/sdram-unused.inc b/src/mainboard/google/oak/sdram_inf/sdram-unused.inc
new file mode 100644
index 0000000..21b2859
--- /dev/null
+++ b/src/mainboard/google/oak/sdram_inf/sdram-unused.inc
@@ -0,0 +1,3 @@
+{
+ .type = TYPE_INVALID,
+},
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