[coreboot-gerrit] New patch to review for coreboot: mediatek/mt8173: add APLL clock setting

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13090

-gerrit

commit 0f8907fde84c2be7f09ff7b7012d09dfca1c244c
Author: Koro Chen <koro.chen at mediatek.com>
Date:   Tue Aug 4 16:16:46 2015 +0800

    mediatek/mt8173: add APLL clock setting
    
    Add a new function mt_pll_set_aud_div() to set APLL for audio I2S.
    The function is called by mainboard's configure_audio().
    
    BRANCH=chromeos-2015.07
    BUG=chrome-os-partner:41507
    TEST=build and verified pass on oak board
    
    Change-Id: Ia3c2f250627028422a7427b93d78d49545eb7a75
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: bb18943f5e74af7723bd4e01d4da96c0b153a0f6
    Original-Change-Id: I7996a8048f2e54ab09093cca3c8bc7447b61170f
    Original-Signed-off-by: Koro Chen <koro.chen at mediatek.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297225
    Original-Commit-Ready: Yidi Lin <yidi.lin at mediatek.com>
    Original-Tested-by: Yidi Lin <yidi.lin at mediatek.com>
    Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
---
 src/soc/mediatek/mt8173/include/soc/pll.h |  1 +
 src/soc/mediatek/mt8173/pll.c             | 34 +++++++++++++++++++++++++++++++
 2 files changed, 35 insertions(+)

diff --git a/src/soc/mediatek/mt8173/include/soc/pll.h b/src/soc/mediatek/mt8173/include/soc/pll.h
index d41e2ae..aa9c8bb 100644
--- a/src/soc/mediatek/mt8173/include/soc/pll.h
+++ b/src/soc/mediatek/mt8173/include/soc/pll.h
@@ -283,5 +283,6 @@ enum {
 
 void mt_pll_post_init(void);
 void mt_pll_init(void);
+void mt_pll_set_aud_div(u32 rate);
 
 #endif /* SOC_MEDIATEK_MT8173_PLL_H */
diff --git a/src/soc/mediatek/mt8173/pll.c b/src/soc/mediatek/mt8173/pll.c
index 3617ee9..4f386c0 100644
--- a/src/soc/mediatek/mt8173/pll.c
+++ b/src/soc/mediatek/mt8173/pll.c
@@ -454,3 +454,37 @@ void mt_pll_post_init(void)
 	/* NOTICE: raise Vproc voltage before raise ARMPLL frequency */
 	write32(&mt8173_infracfg->top_ckmuxsel, (1 << 2) | 1);
 }
+
+void mt_pll_set_aud_div(u32 rate)
+{
+	u32 mclk_div;
+	u32 apll_clock = APLL2_CK_HZ;
+	int apll1 = 0;
+
+	if (rate % 11025 == 0) {
+		/* use APLL1 instead */
+		apll1 = 1;
+		apll_clock = APLL1_CK_HZ;
+	}
+	/* I2S1 clock */
+	mclk_div = (apll_clock / 256 / rate) - 1;
+	assert(apll_clock == rate * 256 * (mclk_div + 1));
+
+	if (apll1) {
+		/* mclk */
+		clrbits_le32(&mt8173_topckgen->clk_auddiv_0, 1 << 5);
+		clrsetbits_le32(&mt8173_topckgen->clk_auddiv_1, 0xff << 8,
+				mclk_div << 8);
+		/* bclk */
+		clrsetbits_le32(&mt8173_topckgen->clk_auddiv_0, 0xf << 24,
+				7 << 24);
+	} else {
+		/* mclk */
+		setbits_le32(&mt8173_topckgen->clk_auddiv_0, 1 << 5);
+		clrsetbits_le32(&mt8173_topckgen->clk_auddiv_2, 0xff << 8,
+				mclk_div << 8);
+		/* bclk */
+		clrsetbits_le32(&mt8173_topckgen->clk_auddiv_0, 0xf << 28,
+				7 << 28);
+	}
+}