[coreboot-gerrit] Patch set updated for coreboot: mediatek/mt8173: Add RTC driver
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Thu Jan 21 11:22:23 CET 2016
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12616
-gerrit
commit d9aa46654ebf544dad1896bb36f36aa5b3d251cf
Author: Tianping Fang <tianping.fang at mediatek.com>
Date: Fri Jul 31 17:10:58 2015 +0800
mediatek/mt8173: Add RTC driver
BUG=none
TEST=emerge-oak coreboot
BRANCH=none
Change-Id: I03740ce1afeb8607891fff61110a40dd98b80bdc
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: 9b0cc22cb9e2010e28e854d9984c11149a71ae0b
Original-Change-Id: I6d6482a75cc40ed6183ee115d5d866257afa24af
Original-Signed-off-by: Tianping Fang <tianping.fang at mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292676
Original-Commit-Ready: Yidi Lin <yidi.lin at mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin at mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
---
src/soc/mediatek/mt8173/Makefile.inc | 2 +-
src/soc/mediatek/mt8173/bootblock.c | 3 +
src/soc/mediatek/mt8173/include/soc/rtc.h | 184 +++++++++++++++++
src/soc/mediatek/mt8173/rtc.c | 317 ++++++++++++++++++++++++++++++
4 files changed, 505 insertions(+), 1 deletion(-)
diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc
index 610d682..efcc032 100644
--- a/src/soc/mediatek/mt8173/Makefile.inc
+++ b/src/soc/mediatek/mt8173/Makefile.inc
@@ -26,7 +26,7 @@ bootblock-$(CONFIG_DRIVERS_UART) += uart.c
endif
bootblock-y += gpio.c gpio_init.c pmic_wrap.c mt6391.c
-bootblock-y += wdt.c
+bootblock-y += wdt.c rtc.c
bootblock-y += mmu_operations.c
################################################################################
diff --git a/src/soc/mediatek/mt8173/bootblock.c b/src/soc/mediatek/mt8173/bootblock.c
index 7fe879c..ac1fd3a 100644
--- a/src/soc/mediatek/mt8173/bootblock.c
+++ b/src/soc/mediatek/mt8173/bootblock.c
@@ -17,6 +17,7 @@
#include <soc/mmu_operations.h>
#include <soc/mt6391.h>
#include <soc/pll.h>
+#include <soc/rtc.h>
#include <soc/wdt.h>
void bootblock_soc_init(void)
@@ -33,4 +34,6 @@ void bootblock_soc_init(void)
/* init watch dog, will disable AP watch dog */
mtk_wdt_init();
+
+ rtc_boot();
}
diff --git a/src/soc/mediatek/mt8173/include/soc/rtc.h b/src/soc/mediatek/mt8173/include/soc/rtc.h
new file mode 100644
index 0000000..dd3546a
--- /dev/null
+++ b/src/soc/mediatek/mt8173/include/soc/rtc.h
@@ -0,0 +1,184 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_MEDIATEK_MT8173_RTC_H
+#define SOC_MEDIATEK_MT8173_RTC_H
+
+#include <stdint.h>
+#include "mt6391.h"
+
+/*
+ * Default values for RTC initialization
+ * Year (YEA) : 1970 ~ 2037
+ * Month (MTH) : 1 ~ 12
+ * Day of Month (DOM): 1 ~ 31
+ */
+
+enum {
+ RTC_DEFAULT_YEA = 2010,
+ RTC_DEFAULT_MTH = 1,
+ RTC_DEFAULT_DOM = 1,
+ RTC_DEFAULT_DOW = 5
+};
+
+enum {
+ RTC_2SEC_REBOOT_ENABLE = 1,
+ RTC_2SEC_MODE = 2
+};
+
+/* RTC registers */
+enum {
+ RTC_BBPU = 0xE000,
+ RTC_IRQ_STA = 0xE002,
+ RTC_IRQ_EN = 0xE004,
+ RTC_CII_EN = 0xE006
+};
+
+enum {
+ RTC_TC_SEC = 0xE00A,
+ RTC_TC_MIN = 0xE00C,
+ RTC_TC_HOU = 0xE00E,
+ RTC_TC_DOM = 0xE010,
+ RTC_TC_DOW = 0xE012,
+ RTC_TC_MTH = 0xE014,
+ RTC_TC_YEA = 0xE016
+};
+
+enum {
+ RTC_AL_SEC = 0xE018,
+ RTC_AL_MIN = 0xE01A,
+ RTC_AL_HOU = 0xE01C,
+ RTC_AL_DOM = 0xE01E,
+ RTC_AL_DOW = 0xE020,
+ RTC_AL_MTH = 0xE022,
+ RTC_AL_YEA = 0xE024,
+ RTC_AL_MASK = 0xE008
+};
+
+enum {
+ RTC_OSC32CON = 0xE026,
+ RTC_CON = 0xE03E,
+ RTC_WRTGR = 0xE03C
+};
+
+enum {
+ RTC_POWERKEY1 = 0xE028,
+ RTC_POWERKEY2 = 0xE02A
+};
+
+enum {
+ RTC_PDN1 = 0xE02C,
+ RTC_PDN2 = 0xE02E,
+ RTC_SPAR0 = 0xE030,
+ RTC_SPAR1 = 0xE032,
+ RTC_PROT = 0xE036,
+ RTC_DIFF = 0xE038,
+ RTC_CALI = 0xE03A
+};
+
+enum {
+ RTC_OSC32CON_UNLOCK1 = 0x1A57,
+ RTC_OSC32CON_UNLOCK2 = 0x2B68
+};
+
+enum {
+ RTC_PROT_UNLOCK1 = 0x586A,
+ RTC_PROT_UNLOCK2 = 0x9136
+};
+
+enum {
+ RTC_BBPU_PWREN = 1U << 0,
+ RTC_BBPU_BBPU = 1U << 2,
+ RTC_BBPU_AUTO = 1U << 3,
+ RTC_BBPU_CLRPKY = 1U << 4,
+ RTC_BBPU_RELOAD = 1U << 5,
+ RTC_BBPU_CBUSY = 1U << 6,
+
+ RTC_CBUSY_TIMEOUT_US = 800
+};
+
+enum {
+ RTC_BBPU_KEY = 0x43 << 8
+};
+
+enum {
+ RTC_IRQ_STA_AL = 1U << 0,
+ RTC_IRQ_STA_TC = 1U << 1,
+ RTC_IRQ_STA_LP = 1U << 3
+};
+
+enum {
+ RTC_IRQ_EN_AL = 1U << 0,
+ RTC_IRQ_EN_TC = 1U << 1,
+ RTC_IRQ_EN_ONESHOT = 1U << 2,
+ RTC_IRQ_EN_LP = 1U << 3,
+ RTC_IRQ_EN_ONESHOT_AL = RTC_IRQ_EN_ONESHOT | RTC_IRQ_EN_AL
+};
+
+enum {
+ RTC_OSC32CON_AMPEN = 1U << 8,
+ RTC_OSC32CON_LNBUFEN = 1U << 11
+};
+
+enum {
+ RTC_POWERKEY1_KEY = 0xa357,
+ RTC_POWERKEY2_KEY = 0x67d2
+};
+
+enum {
+ RTC_CON_LPEN = 1U << 2,
+ RTC_CON_LPRST = 1U << 3,
+ RTC_CON_CDBO = 1U << 4,
+ RTC_CON_F32KOB = 1U << 5,
+ RTC_CON_GPO = 1U << 6,
+ RTC_CON_GOE = 1U << 7,
+ RTC_CON_GSR = 1U << 8,
+ RTC_CON_GSMT = 1U << 9,
+ RTC_CON_GPEN = 1U << 10,
+ RTC_CON_GPU = 1U << 11,
+ RTC_CON_GE4 = 1U << 12,
+ RTC_CON_GE8 = 1U << 13,
+ RTC_CON_GPI = 1U << 14,
+ RTC_CON_LPSTA_RAW = 1U << 15
+};
+
+enum {
+ RTC_CALI_BBPU_2SEC_EN = 1U << 8,
+ RTC_CALI_BBPU_2SEC_MODE_SHIFT = 9,
+ RTC_CALI_BBPU_2SEC_MODE_MSK = 3U << RTC_CALI_BBPU_2SEC_MODE_SHIFT,
+ RTC_CALI_BBPU_2SEC_STAT = 1U << 11
+};
+
+enum {
+ RTC_SPAR0_32K_LESS = 1U << 6
+};
+
+enum {
+ RTC_MIN_YEAR = 1968,
+ RTC_BASE_YEAR = 1900,
+ RTC_MIN_YEAR_OFFSET = RTC_MIN_YEAR - RTC_BASE_YEAR,
+
+ RTC_NUM_YEARS = 128
+};
+
+enum {
+ RTC_STATE_REBOOT = 0,
+ RTC_STATE_RECOVER = 1,
+ RTC_STATE_INIT = 2
+};
+
+void rtc_boot(void);
+
+#endif /* SOC_MEDIATEK_MT8173_RTC_H */
diff --git a/src/soc/mediatek/mt8173/rtc.c b/src/soc/mediatek/mt8173/rtc.c
new file mode 100644
index 0000000..4147a0f
--- /dev/null
+++ b/src/soc/mediatek/mt8173/rtc.c
@@ -0,0 +1,317 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <assert.h>
+#include <bcd.h>
+#include <console/console.h>
+#include <delay.h>
+#include <rtc.h>
+#include <timer.h>
+
+#include <soc/mt6391.h>
+#include <soc/pmic_wrap.h>
+#include <soc/rtc.h>
+
+#define RTC_GPIO_USER_MASK ((1 << 13) - (1 << 8))
+
+/* ensure rtc write success */
+static inline int rtc_busy_wait(void)
+{
+ struct stopwatch sw;
+ u16 bbpu;
+
+ stopwatch_init_usecs_expire(&sw, RTC_CBUSY_TIMEOUT_US);
+
+ do {
+ pwrap_read(RTC_BBPU, &bbpu);
+ /* Time > 1sec, time out and set recovery mode enable.*/
+ if (stopwatch_expired(&sw)) {
+ printk(BIOS_INFO, "[RTC] BBPU CBUSY time out !!\n");
+ return 0;
+ }
+ } while (bbpu & RTC_BBPU_CBUSY);
+
+ return 1;
+}
+
+static int write_trigger(void)
+{
+ pwrap_write(RTC_WRTGR, 1);
+ return rtc_busy_wait();
+}
+
+/* unlock rtc write interface */
+static int writeif_unlock(void)
+{
+ pwrap_write(RTC_PROT, RTC_PROT_UNLOCK1);
+ if (!write_trigger())
+ return 0;
+ pwrap_write(RTC_PROT, RTC_PROT_UNLOCK2);
+ if (!write_trigger())
+ return 0;
+
+ return 1;
+}
+
+/* set rtc time */
+int rtc_set(const struct rtc_time *time)
+{
+ return -1;
+}
+
+/* get rtc time */
+int rtc_get(struct rtc_time *time)
+{
+ u16 value;
+
+ pwrap_read(RTC_TC_SEC, &value);
+ time->sec = value;
+ pwrap_read(RTC_TC_MIN, &value);
+ time->min = value;
+ pwrap_read(RTC_TC_HOU, &value);
+ time->hour = value;
+ pwrap_read(RTC_TC_DOM, &value);
+ time->mday = value;
+ pwrap_read(RTC_TC_MTH, &value);
+ time->mon = value;
+ pwrap_read(RTC_TC_YEA, &value);
+ time->year = (value + RTC_MIN_YEAR_OFFSET) % 100;
+
+ return 0;
+}
+
+/* set rtc xosc setting */
+static void rtc_xosc_write(u16 val)
+{
+ pwrap_write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK1);
+ udelay(200);
+ pwrap_write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK2);
+ udelay(200);
+
+ pwrap_write(RTC_OSC32CON, val);
+ udelay(200);
+ mt6391_write(RTC_BBPU, RTC_BBPU_KEY | RTC_BBPU_RELOAD, 0, 0);
+ write_trigger();
+}
+
+/* initialize rtc related registers */
+static int rtc_reg_init(void)
+{
+ u16 irqsta;
+
+ pwrap_write(RTC_IRQ_EN, 0);
+ pwrap_write(RTC_CII_EN, 0);
+ pwrap_write(RTC_AL_MASK, 0);
+ pwrap_write(RTC_AL_YEA, 1970 - RTC_MIN_YEAR);
+ pwrap_write(RTC_AL_MTH, 1);
+ pwrap_write(RTC_AL_DOM, 1);
+ pwrap_write(RTC_AL_DOW, 4);
+ pwrap_write(RTC_AL_HOU, 0);
+ pwrap_write(RTC_AL_MIN, 0);
+ pwrap_write(RTC_AL_SEC, 0);
+
+ pwrap_write(RTC_DIFF, 0);
+ pwrap_write(RTC_CALI, 0);
+ if (!write_trigger())
+ return 0;
+
+ pwrap_read(RTC_IRQ_STA, &irqsta); /* read clear */
+
+ /* init time counters after resetting RTC_DIFF and RTC_CALI */
+ pwrap_write(RTC_TC_YEA, RTC_DEFAULT_YEA - RTC_MIN_YEAR);
+ pwrap_write(RTC_TC_MTH, RTC_DEFAULT_MTH);
+ pwrap_write(RTC_TC_DOM, RTC_DEFAULT_DOM);
+ pwrap_write(RTC_TC_DOW, RTC_DEFAULT_DOW);
+ pwrap_write(RTC_TC_HOU, 0);
+ pwrap_write(RTC_TC_MIN, 0);
+ pwrap_write(RTC_TC_SEC, 0);
+
+ return write_trigger();
+}
+
+/* initialize rtc related gpio */
+static int rtc_gpio_init(void)
+{
+ u16 con;
+
+ mt6391_gpio_set_pull(3, MT6391_GPIO_PULL_DISABLE,
+ MT6391_GPIO_PULL_DOWN); /* RTC_32K1V8 */
+
+ /* Export 32K clock RTC_32K2V8 */
+ pwrap_read(RTC_CON, &con);
+ con &= (RTC_CON_LPSTA_RAW | RTC_CON_LPRST | RTC_CON_LPEN);
+ con |= (RTC_CON_GPEN | RTC_CON_GOE);
+ con &= ~(RTC_CON_F32KOB);
+ pwrap_write(RTC_CON, con);
+ return write_trigger();
+}
+
+/* set xosc mode */
+static void rtc_osc_init(void)
+{
+ u16 con;
+
+ /* enable 32K export */
+ rtc_gpio_init();
+
+ pwrap_write(PMIC_RG_TOP_CKTST2, 0x0);
+ pwrap_read(RTC_OSC32CON, &con);
+ if ((con & 0x1f) != 0x0) /* check XOSCCALI */
+ rtc_xosc_write(0x3);
+}
+
+/* low power detect setting */
+static int rtc_lpd_init(void)
+{
+ mt6391_write(RTC_CON, RTC_CON_LPEN, RTC_CON_LPRST, 0);
+ if (!write_trigger())
+ return 0;
+
+ mt6391_write(RTC_CON, RTC_CON_LPRST, 0, 0);
+ if (!write_trigger())
+ return 0;
+
+ mt6391_write(RTC_CON, 0, RTC_CON_LPRST, 0);
+ if (!write_trigger())
+ return 0;
+
+ return 1;
+}
+
+/* rtc init check */
+static int rtc_init(u8 recover)
+{
+ printk(BIOS_INFO, "[RTC] %s recovery: %d\n", __func__, recover);
+
+ if (!writeif_unlock())
+ return 0;
+
+ if (!rtc_gpio_init())
+ return 0;
+
+ /* Use SW to detect 32K mode instead of HW */
+ if (recover)
+ mt6391_write(PMIC_RG_CHRSTATUS, 0x4, 0x1, 9);
+
+ rtc_xosc_write(0x3);
+
+ if (recover)
+ mdelay(1000);
+
+ /* write powerkeys */
+ pwrap_write(RTC_POWERKEY1, RTC_POWERKEY1_KEY);
+ pwrap_write(RTC_POWERKEY2, RTC_POWERKEY2_KEY);
+ if (!write_trigger())
+ return 0;
+
+ if (recover)
+ mt6391_write(PMIC_RG_CHRSTATUS, 0, 0x4, 9);
+
+ rtc_xosc_write(0);
+
+ if (!rtc_reg_init())
+ return 0;
+ if (!rtc_lpd_init())
+ return 0;
+
+ return 1;
+}
+
+/* enable rtc bbpu */
+static void rtc_bbpu_power_on(void)
+{
+ u16 bbpu;
+ int ret;
+
+ /* pull PWRBB high */
+ bbpu = RTC_BBPU_KEY | RTC_BBPU_AUTO | RTC_BBPU_BBPU | RTC_BBPU_PWREN;
+ pwrap_write(RTC_BBPU, bbpu);
+ ret = write_trigger();
+ printk(BIOS_INFO, "[RTC] %s write_trigger=%d\n", __func__, ret);
+
+ /* enable DCXO to transform external 32KHz clock to 26MHz clock
+ directly sent to SoC */
+ mt6391_write(PMIC_RG_DCXO_FORCE_MODE1, BIT(11), 0, 0);
+ mt6391_write(PMIC_RG_DCXO_POR2_CON3,
+ BIT(8) | BIT(9) | BIT(10) | BIT(11), 0, 0);
+ mt6391_write(PMIC_RG_DCXO_CON2,
+ BIT(1) | BIT(3) | BIT(5) | BIT(6), 0, 0);
+
+ pwrap_read(RTC_BBPU, &bbpu);
+ printk(BIOS_INFO, "[RTC] %s done BBPU=%#x\n", __func__, bbpu);
+
+ /* detect hw clock done,close RG_RTC_75K_PDN for low power setting. */
+ mt6391_write(PMIC_RG_TOP_CKPDN2, 0x1, 0, 14);
+}
+
+static u8 rtc_check_state(void)
+{
+ u16 con;
+ u16 pwrky1;
+ u16 pwrky2;
+
+ pwrap_read(RTC_CON, &con);
+ pwrap_read(RTC_POWERKEY1, &pwrky1);
+ pwrap_read(RTC_POWERKEY2, &pwrky2);
+
+ if (con & RTC_CON_LPSTA_RAW)
+ return RTC_STATE_INIT;
+
+ if (!rtc_busy_wait())
+ return RTC_STATE_RECOVER;
+
+ if (!writeif_unlock())
+ return RTC_STATE_RECOVER;
+
+ if (pwrky1 != RTC_POWERKEY1_KEY || pwrky2 != RTC_POWERKEY2_KEY)
+ return RTC_STATE_INIT;
+ else
+ return RTC_STATE_REBOOT;
+}
+
+/* the rtc boot flow entry */
+void rtc_boot(void)
+{
+ u16 bbpu;
+ u16 con;
+ u16 irqsta;
+
+ pwrap_write(PMIC_RG_TOP_CKPDN, 0);
+ pwrap_write(PMIC_RG_TOP_CKPDN2, 0);
+
+ switch (rtc_check_state()) {
+ case RTC_STATE_REBOOT:
+ mt6391_write(RTC_BBPU, RTC_BBPU_KEY | RTC_BBPU_RELOAD, 0, 0);
+ write_trigger();
+ rtc_osc_init();
+ break;
+ case RTC_STATE_RECOVER:
+ rtc_init(1);
+ break;
+ case RTC_STATE_INIT:
+ default:
+ if (!rtc_init(0))
+ rtc_init(1);
+ break;
+ }
+
+ pwrap_read(RTC_IRQ_STA, &irqsta); /* Read clear */
+ pwrap_read(RTC_BBPU, &bbpu);
+ pwrap_read(RTC_CON, &con);
+
+ printk(BIOS_INFO, "[RTC] irqsta = %x", irqsta);
+ printk(BIOS_INFO, " bbpu = %#x, con = %#x\n", bbpu, con);
+ rtc_bbpu_power_on();
+}
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