[coreboot-gerrit] Patch set updated for coreboot: soc/braswell: Add interface to program USB2_COMPBG register
Hannah Williams (hannah.williams@intel.com)
gerrit at coreboot.org
Tue Jan 19 20:10:56 CET 2016
Hannah Williams (hannah.williams at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12739
-gerrit
commit 20f74e2782210ccae643fccb12470d61522b9af3
Author: shkim <sh_.kim at samsung.com>
Date: Tue Sep 22 17:53:58 2015 +0900
soc/braswell: Add interface to program USB2_COMPBG register
Add interface to program USB2_COMPBG register to set
HS_DISC_BG and HS_SQ reference voltage for each project.
TEST=Get build success and do EFT test
Original-Reviewed-on: https://chromium-review.googlesource.com/300846
Original-Reviewed-by: Shawn N <shawnn at chromium.org>
Original-Tested-by: shkim <sh_.kim at samsung.com>
Change-Id: If2201829e1a16b4f9916547f08c24e9291358325
Signed-off-by: Kenji Chen <kenji.chen at intel.com>
Signed-off-by: shkim <sh_.kim at samsung.com>
Signed-off-by: Hannah Williams <hannah.williams at intel.com>
---
src/soc/intel/braswell/chip.h | 18 ++++++++
src/soc/intel/braswell/include/soc/iosf.h | 5 +++
src/soc/intel/braswell/iosf.c | 15 ++++++-
src/soc/intel/braswell/xhci.c | 68 +++++++++++++++++++++++++++++++
4 files changed, 105 insertions(+), 1 deletion(-)
diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h
index 0f3c1d0..e85d958 100644
--- a/src/soc/intel/braswell/chip.h
+++ b/src/soc/intel/braswell/chip.h
@@ -33,6 +33,17 @@
#define MEM_DDR3 0
#define MEM_LPDDR3 1
+enum usb_comp_bg_value {
+ USB_COMP_BG_575_MV = 7,
+ USB_COMP_BG_650_MV = 6,
+ USB_COMP_BG_550_MV = 5,
+ USB_COMP_BG_537_MV = 4,
+ USB_COMP_BG_625_MV = 3,
+ USB_COMP_BG_700_MV = 2,
+ USB_COMP_BG_600_MV = 1,
+ USB_COMP_BG_675_MV = 0,
+};
+
struct soc_intel_braswell_config {
uint8_t enable_xdp_tap;
uint8_t clkreq_enable;
@@ -57,6 +68,13 @@ struct soc_intel_braswell_config {
/* Allow PCIe devices to wake system from suspend. */
int pcie_wake_enable;
+ /* Program USB2_COMPBG register.
+ * [10:7] - select vref to AFE port
+ * x111 - 575mV, x110 - 650mV, x101 - 550mV, x100 - 537.5mV,
+ * x011 - 625mV, x010 - 700mV, x001 - 600mV, x000 - 675mV
+ */
+ enum usb_comp_bg_value usb_comp_bg;
+
/*
* The following fields come from fsp_vpd.h .aka. VpdHeader.h.
* These are configuration values that are passed to FSP during
diff --git a/src/soc/intel/braswell/include/soc/iosf.h b/src/soc/intel/braswell/include/soc/iosf.h
index add602f..e6758a6 100644
--- a/src/soc/intel/braswell/include/soc/iosf.h
+++ b/src/soc/intel/braswell/include/soc/iosf.h
@@ -69,6 +69,8 @@ uint32_t iosf_port58_read(int reg);
void iosf_port58_write(int reg, uint32_t val);
uint32_t iosf_scc_read(int reg);
void iosf_scc_write(int reg, uint32_t val);
+uint32_t iosf_usbphy_read(int reg);
+void iosf_usbphy_write(int reg, uint32_t val);
#if ENV_RAMSTAGE
uint64_t reg_script_read_iosf(struct reg_script_context *ctx);
@@ -91,6 +93,7 @@ void reg_script_write_iosf(struct reg_script_context *ctx);
#define IOSF_PORT_0x5a 0x5a
#define IOSF_PORT_USHPHY 0x61 /* USB XHCI PHY */
#define IOSF_PORT_SCC 0x63 /* Storage Control Cluster */
+#define IOSF_PORT_USBPHY 0x43 /* USB PHY */
#define IOSF_PORT_LPSS 0xa0 /* LPSS - Low Power Subsystem */
#define IOSF_PORT_0xa2 0xa2
#define IOSF_PORT_SSUS 0xa8 /* SUS */
@@ -109,6 +112,8 @@ void reg_script_write_iosf(struct reg_script_context *ctx);
#define IOSF_OP_WRITE_0x58 (IOSF_OP_READ_0x58 | 1)
#define IOSF_OP_READ_SCC 0x06
#define IOSF_OP_WRITE_SCC (IOSF_OP_READ_SCC | 1)
+#define IOSF_OP_READ_USBPHY 0x06
+#define IOSF_OP_WRITE_USBPHY (IOSF_OP_READ_USBPHY | 1)
/*
* BUNIT Registers.
diff --git a/src/soc/intel/braswell/iosf.c b/src/soc/intel/braswell/iosf.c
index 1e7b924..98d1610 100644
--- a/src/soc/intel/braswell/iosf.c
+++ b/src/soc/intel/braswell/iosf.c
@@ -122,6 +122,15 @@ void iosf_scc_write(int reg, uint32_t val)
return iosf_write_port(IOSF_WRITE(SCC), reg, val);
}
+uint32_t iosf_usbphy_read(int reg)
+{
+ return iosf_read_port(IOSF_READ(USBPHY), reg);
+}
+
+void iosf_usbphy_write(int reg, uint32_t val)
+{
+ return iosf_write_port(IOSF_WRITE(USBPHY), reg, val);
+}
#if ENV_RAMSTAGE
uint64_t reg_script_read_iosf(struct reg_script_context *ctx)
@@ -140,6 +149,8 @@ uint64_t reg_script_read_iosf(struct reg_script_context *ctx)
return iosf_port58_read(step->reg);
case IOSF_PORT_SCC:
return iosf_scc_read(step->reg);
+ case IOSF_PORT_USBPHY:
+ return iosf_usbphy_read(step->reg);
default:
printk(BIOS_DEBUG, "No read support for IOSF port 0x%x.\n",
step->id);
@@ -169,7 +180,9 @@ void reg_script_write_iosf(struct reg_script_context *ctx)
case IOSF_PORT_SCC:
iosf_scc_write(step->reg, step->value);
break;
-
+ case IOSF_PORT_USBPHY:
+ iosf_usbphy_write(step->reg, step->value);
+ break;
default:
printk(BIOS_DEBUG, "No write support for IOSF port 0x%x.\n",
step->id);
diff --git a/src/soc/intel/braswell/xhci.c b/src/soc/intel/braswell/xhci.c
new file mode 100644
index 0000000..9ae1a2d
--- /dev/null
+++ b/src/soc/intel/braswell/xhci.c
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <arch/acpi.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <stdint.h>
+#include <reg_script.h>
+
+#include <soc/iomap.h>
+#include <soc/iosf.h>
+#include <soc/pci_devs.h>
+#include <soc/pm.h>
+#include <soc/ramstage.h>
+#include <soc/xhci.h>
+
+#include "chip.h"
+
+static void xhci_init(device_t dev)
+{
+ printk(BIOS_SPEW, "%s/%s ( %s )\n",
+ __FILE__, __func__, dev_name(dev));
+
+ struct soc_intel_braswell_config *config = dev->chip_info;
+
+ if (config && config->usb_comp_bg) {
+ struct reg_script ops[] = {
+ REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_COMPBG,
+ config->usb_comp_bg),
+ REG_SCRIPT_END
+ };
+ printk(BIOS_INFO, "Override USB2_COMPBG to: 0x%X\n", config->usb_comp_bg);
+ reg_script_run(ops);
+ }
+}
+
+static struct device_operations xhci_device_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = xhci_init,
+ .ops_pci = &soc_pci_ops,
+};
+
+static const struct pci_driver soc_xhci __pci_driver = {
+ .ops = &xhci_device_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = XHCI_DEVID
+};
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