[coreboot-gerrit] Patch set updated for coreboot: intel/skylake: Disable SaGv in recovery mode

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12998

-gerrit

commit 2fbe19576bf968eb58143b96e5c0fe74960b97e1
Author: haridhar <haridhar.kalvala at intel.com>
Date:   Mon Dec 7 16:50:37 2015 +0530

    intel/skylake: Disable SaGv in recovery mode
    
    This patch disables the SaGv feature in recovery mode. Since the memory
    training happens at both low and high frequency points when SaGv is
    enabled, recovery mode boot time increases by 5 seconds. To reduce this
    5 second increase, the SaGv feature is disabled in recovery mode.
    
    The value "0" here means SaGv disable.
    Following is the table for same.
    
    0=Disabled (SaGv disabled)
    1=FixedLow (Fixed to low frequency)
    2=FixedHigh (Fixed to High frequency)
    3=Enabled (SaGv Enabled. Dynamically changes)
    
    BRANCH=None
    BUG=chrome-os-partner:48534
    TEST=Built for kunimitsu.
    Results show recovery mode boot time
    is not affected (not increased).
    
    Change-Id: I77412a73a183a5dbecf5564a22acc6e63865123e
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: dc586079052acf9af573b68dff910386cd43484d
    Original-Change-Id: Ice3e1a630e119d40d3df52e3a53ca984e999ab0b
    Original-Signed-off-by: haridhar <haridhar.kalvala at intel.com>
    Original-Signed-off-by: Somayaji, Vishwanath <vishwanath.somayaji at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/315759
    Original-Commit-Ready: Haridhar Kalvala <haridhar.kalvala at intel.com>
    Original-Tested-by: Haridhar Kalvala <haridhar.kalvala at intel.com>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-by: Subrata Banik <subrata.banik at intel.com>
    Original-Reviewed-by: Haridhar Kalvala <haridhar.kalvala at intel.com>
---
 src/soc/intel/skylake/romstage/romstage.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index 31f7fc2..b872d39 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -90,7 +90,10 @@ void soc_memory_init_params(struct romstage_params *params,
 	upd->IedSize = CONFIG_IED_REGION_SIZE;
 	upd->ProbelessTrace = config->ProbelessTrace;
 	upd->EnableTraceHub = config->EnableTraceHub;
-	upd->SaGv = config->SaGv;
+	if (recovery_mode_enabled())
+		upd->SaGv = 0; /* Disable SaGv in recovery mode. */
+	else
+		upd->SaGv = config->SaGv;
 	upd->RMT = config->Rmt;
 	upd->DdrFreqLimit = config->DdrFreqLimit;
 }