[coreboot-gerrit] Patch set updated for coreboot: google/glados: Set FSP params for min assertion widths and serirq

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13008

-gerrit

commit 46bafe945309da2e04d5ff2ee8c70b962d229c2b
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Jan 7 16:55:31 2016 -0800

    google/glados: Set FSP params for min assertion widths and serirq
    
    - Enable serial irq configuration in FSP.
    - Set minimum assertion width values for FSP to configure.
    - Set I2C4 voltage to 1.8V.
    - Enable SaGv feature to dynamically train memory frequency.
    - Disable Deep S3 to match chell so DeepSx story is consistent
    on skylake-y boards.
    
    BUG=chrome-os-partner:47688
    BRANCH=none
    TEST=emerge-glados coreboot (tested on chell board)
    
    Change-Id: Ied6bda6a3f2108df7167e0970abe71977d8d2a5c
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: fbf353288edc9629ad03b17d0a582e3042d5a5e1
    Original-Change-Id: I1619dd5316060793f38b74f8f0bcaf23d8ab2552
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/321211
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/glados/devicetree.cb | 35 +++++++++++++++++++------------
 1 file changed, 22 insertions(+), 13 deletions(-)

diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index 62d2553..03c46f4 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -1,7 +1,7 @@
 chip soc/intel/skylake
 
 	# Enable deep Sx states
-	register "deep_s3_enable" = "1"
+	register "deep_s3_enable" = "0"
 	register "deep_s5_enable" = "1"
 	register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
 
@@ -44,6 +44,12 @@ chip soc/intel/skylake
 	register "Device4Enable" = "1"
 	register "HeciEnabled" = "0"
 	register "FspSkipMpInit" = "1"
+	register "SaGv" = "3"
+	register "SerialIrqConfigSirqEnable" = "1"
+	register "PmConfigSlpS3MinAssert" = "2"        # 50ms
+	register "PmConfigSlpS4MinAssert" = "1"        # 1s
+	register "PmConfigSlpSusMinAssert" = "1"       # 500ms
+	register "PmConfigSlpAMinAssert" = "3"         # 2s
 
 	# VR Settings Configuration for 5 Domains
 	#+----------------+-------+-------+-------------+-------------+-------+
@@ -144,20 +150,23 @@ chip soc/intel/skylake
 	register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # Type-A Port 2
 
 	# Must leave UART0 enabled or SD/eMMC will not work as PCI
-	register "SerialIoDevMode" = "{ \
-		[PchSerialIoIndexI2C0]  = PchSerialIoPci, \
-		[PchSerialIoIndexI2C1]  = PchSerialIoPci, \
-		[PchSerialIoIndexI2C2]  = PchSerialIoDisabled, \
-		[PchSerialIoIndexI2C3]  = PchSerialIoDisabled, \
-		[PchSerialIoIndexI2C4]  = PchSerialIoPci, \
-		[PchSerialIoIndexI2C5]  = PchSerialIoDisabled, \
-		[PchSerialIoIndexSpi0]  = PchSerialIoDisabled, \
-		[PchSerialIoIndexSpi1]  = PchSerialIoDisabled, \
-		[PchSerialIoIndexUart0] = PchSerialIoPci, \
-		[PchSerialIoIndexUart1] = PchSerialIoDisabled, \
-		[PchSerialIoIndexUart2] = PchSerialIoPci, \
+	register "SerialIoDevMode" = "{
+		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C1]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C2]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C3]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C4]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C5]  = PchSerialIoDisabled,
+		[PchSerialIoIndexSpi0]  = PchSerialIoDisabled,
+		[PchSerialIoIndexSpi1]  = PchSerialIoDisabled,
+		[PchSerialIoIndexUart0] = PchSerialIoPci,
+		[PchSerialIoIndexUart1] = PchSerialIoDisabled,
+		[PchSerialIoIndexUart2] = PchSerialIoPci,
 	}"
 
+	# I2C4 is 1.8V
+	register "SerialIoI2cVoltage[4]" = "1"
+
 	device cpu_cluster 0 on
 		device lapic 0 on end
 	end