[coreboot-gerrit] Patch set updated for coreboot: google/lars: SPD changes for EVT board

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12996

-gerrit

commit 3d962f8d937392d0ce48fb8ddb420b46ef8b2170
Author: david <david_wu at quantatw.com>
Date:   Wed Dec 23 20:12:06 2015 +0800

    google/lars: SPD changes for EVT board
    
    Update Memory IDs for EVT board
    
    BUG=None
    BRANCH=lars
    TEST=Build and boot lars
    
    Change-Id: I8c0c731fc3a8eec0cb558137e9db90170debf2c6
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: a95fbf063b2e41d551171228a1ea8cbcfdcaecc8
    Original-Change-Id: I2be8a7db99f17ea2968d7e4c5de83cc3e4cbcd14
    Original-Signed-off-by: David Wu <David_Wu at quantatw.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/319622
    Original-Commit-Ready: David Wu <david_wu at quantatw.com>
    Original-Tested-by: David Wu <david_wu at quantatw.com>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/lars/spd/Makefile.inc | 6 +++---
 src/mainboard/google/lars/spd/spd.c        | 3 ++-
 src/mainboard/google/lars/spd/spd.h        | 4 +++-
 3 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/google/lars/spd/Makefile.inc b/src/mainboard/google/lars/spd/Makefile.inc
index 4b9c376..7f49cdb 100644
--- a/src/mainboard/google/lars/spd/Makefile.inc
+++ b/src/mainboard/google/lars/spd/Makefile.inc
@@ -21,9 +21,9 @@ SPD_BIN = $(obj)/spd.bin
 SPD_SOURCES  = hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866    # 0b0000 Single Channel 2GB
 SPD_SOURCES += hynix_dimm_H9CCNNNBLTBLAR-NUD-2G-1866    # 0b0001 Dual Channel 8GB
 SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF-1G-1866     # 0b0010 Dual Channel 4GB
-SPD_SOURCES += empty                                    # 0b0011
-SPD_SOURCES += empty                                    # 0b0100
-SPD_SOURCES += empty                                    # 0b0101
+SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF-1G-1866     # 0b0011 Single Channel 2GB
+SPD_SOURCES += hynix_dimm_H9CCNNNBLTBLAR-NUD-2G-1866    # 0b0100 Single Channel 4GB
+SPD_SOURCES += samsung_dimm_K4E6E304EB-EGCF-2G-1866     # 0b0101 Dual Channel 8GB
 SPD_SOURCES += empty                                    # 0b0110
 SPD_SOURCES += empty                                    # 0b0111
 SPD_SOURCES += empty                                    # 0b1000
diff --git a/src/mainboard/google/lars/spd/spd.c b/src/mainboard/google/lars/spd/spd.c
index b8d8cd0..106eb83 100644
--- a/src/mainboard/google/lars/spd/spd.c
+++ b/src/mainboard/google/lars/spd/spd.c
@@ -105,7 +105,8 @@ void mainboard_fill_spd_data(struct pei_data *pei_data)
 	spd_span = spd_index * SPD_LEN;
 	memcpy(pei_data->spd_data[0][0], spd_file + spd_span, SPD_LEN);
 
-	if (spd_index != HYNIX_SINGLE_CHAN) {
+	if (spd_index != MEM_SINGLE_CHAN0 && spd_index != MEM_SINGLE_CHAN3
+		&& spd_index != MEM_SINGLE_CHAN4) {
 		memcpy(pei_data->spd_data[1][0], spd_file + spd_span, SPD_LEN);
 		printk(BIOS_INFO, "Dual channel SPD detected writing second channel\n");
 	}
diff --git a/src/mainboard/google/lars/spd/spd.h b/src/mainboard/google/lars/spd/spd.h
index c4b2b56..d71487b 100644
--- a/src/mainboard/google/lars/spd/spd.h
+++ b/src/mainboard/google/lars/spd/spd.h
@@ -30,5 +30,7 @@
 #define  SPD_PART_LEN		18
 #define SPD_MANU_OFF		148
 
-#define HYNIX_SINGLE_CHAN	0x0
+#define MEM_SINGLE_CHAN0	0x0
+#define MEM_SINGLE_CHAN3	0x3
+#define MEM_SINGLE_CHAN4	0x4
 #endif