[coreboot-gerrit] Patch set updated for coreboot: intel/kunimitsu: Enable FspSkipMpInit token

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12992

-gerrit

commit 1b4d26378ee57208045f0920e1997913ffad75f0
Author: Rizwan Qureshi <rizwan.qureshi at intel.com>
Date:   Thu Nov 19 16:30:18 2015 +0530

    intel/kunimitsu: Enable FspSkipMpInit token
    
    MP init is already handled in coreboot, but it is also part of FSP
    FSP has a implemented a provision to allow FSP to skip MP init and
    let coreboot handle it.
    
    BRANCH=none
    BUG=chrome-os-partner:44805
    TEST=Build and booted in kunimitsu with SkipMpInit enabled from CB.
    
    CQ-DEPEND=CL:310192
    
    Change-Id: Idd9b1424f23765ce227005a322ac72d9e9fc841a
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 5c52d0f0cc5d480c87fababc3316009e3ade6e45
    Original-Change-Id: I9d92046d0237680b8d562814a9a605a36efb9516
    Original-Signed-off-by: Barnali Sarkar <barnali.sarkar at intel.com>
    Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/312926
    Original-Commit-Ready: Preetham Chandrian <preetham.chandrian at intel.com>
    Original-Tested-by: Preetham Chandrian <preetham.chandrian at intel.com>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/intel/kunimitsu/devicetree.cb | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index ffe0662..572dd43 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -126,6 +126,8 @@ chip soc/intel/skylake
 		.voltage_limit = 0x5F0 \
 	}"
 
+	register "FspSkipMpInit" = "1"
+
 	# Enable Root port 1 and 5.
 	register "PcieRpEnable[0]" = "1"
 	register "PcieRpEnable[4]" = "1"