[coreboot-gerrit] Patch merged into coreboot/master: skylake boards: csme: add p2sb device and hecienabled devicetree variable

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 30f53cd3973886fb69a59479231656846e11e5ca
Author: Archana Patni <archana.patni at intel.com>
Date:   Wed Nov 11 01:30:41 2015 +0530

    skylake boards: csme: add p2sb device and hecienabled devicetree variable
    
    The HeciEnabled decides the state of Heci1 at end of boot. Setting to 0
    (default) disables Heci1 and hides the device from OS. It internally uses
    the FSP Psf Unlock policy to disable the Heci1. It also adds the p2sb
    device in the devicetree which is necessary for hiding and unhiding the
    device.
    
    BRANCH=none
    BUG=chrome-os-partner:45618
    TEST=build for kunimitsu.
    
    CQ-DEPEND=CL:*238451
    
    Change-Id: Ieba2ab3b4ac518cce8371069028170ba99aaf079
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: cbefe9d6e9a981594534d346be67a5cd94483d05
    Original-Change-Id: I8c95b5b9b28ba8441ca031f4e9ec523d913990d6
    Original-Signed-off-by: Archana Patni <archana.patni at intel.com>
    Original-Signed-off-by: Subramony Sesha <subramony.sesha at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/311913
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: https://review.coreboot.org/12977
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martinroth at google.com>


See https://review.coreboot.org/12977 for details.

-gerrit