[coreboot-gerrit] Patch merged into coreboot/master: intel/skylake: During RO mode after FSP reset CB lose original state

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit df13c31ed6fdad2cdb6e8e874f26e5cad2ce935f
Author: Subrata Banik <subrata.banik at intel.com>
Date:   Mon Sep 28 15:12:08 2015 +0530

    intel/skylake: During RO mode after FSP reset CB lose original state
    
    CB used to clear recovery status towards romstage end after FSP
    memory init. Later inside FSP silicon init due to HSIO CRC mismatch
    it will request for an additional reset.On next boot system resume
    in dev mode rather than recovery because lost its original state
    due to FSP silicon init reset.
    
    Hence an additional 1 reset require to identify original state.
    With this patch, we will get future platform reset info during romstage
    and restore back recovery request flag so, in next boot CB can maintain
    its original status and avoid 1 extra reboot.
    
    BUG=chrome-os-partner:43517
    BRANCH=none
    TEST= build and booted Kunimitsu and tested RO mode
    
    Change-Id: Ibf86ff2b140cd9ad259eb39987d78177535cd975
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 40ddc21a97b318510116b7d5c4314380778a40f7
    Original-Change-Id: Ia52835f87ef580317e91931aee5dd0119dea8111
    Original-Signed-off-by: Subrata Banik <subrata.banik at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/302257
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: https://review.coreboot.org/12975
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martinroth at google.com>


See https://review.coreboot.org/12975 for details.

-gerrit