[coreboot-gerrit] Patch set updated for coreboot: google/lars: Correct the output for crossystem wpsw_boot

Martin Roth (martinroth@google.com) gerrit at coreboot.org
Sun Jan 17 21:14:19 CET 2016


Martin Roth (martinroth at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12966

-gerrit

commit 84eeaa05a2bc5869222006181176af6cde369917
Author: david <david_wu at quantatw.com>
Date:   Wed Dec 9 15:29:06 2015 +0800

    google/lars: Correct the output for crossystem wpsw_boot
    
    The write protect GPIO is not being configured early enough.
    This is leading to coreboot reading incorrect value, and
    writing the incorrect value in vboot shared file.
    This is leading to "crossystem wpsw_boot" always returning 0
    even with the write protect screw in place during boot.
    
    BRANCH=none
    BUG=chrome-os-partner:48292
    TEST=Build and boot on lars
    
    Change-Id: I28fbbd690ca6efb539422e9ba02f10e07cd35346
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: d229ba9d8934dcb5f22b27ce0ad27601ec87d6ff
    Original-Change-Id: I64f2497a6bb3a50b0f58c67e2ab6751c4836fd89
    Original-Signed-off-by: David Wu <David_Wu at quantatw.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/317130
    Original-Commit-Ready: David Wu <david_wu at quantatw.com>
    Original-Tested-by: David Wu <david_wu at quantatw.com>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/lars/gpio.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/lars/gpio.h b/src/mainboard/google/lars/gpio.h
index acb04ec..5aee237 100755
--- a/src/mainboard/google/lars/gpio.h
+++ b/src/mainboard/google/lars/gpio.h
@@ -226,6 +226,7 @@ static const struct pad_config gpio_table[] = {
 static const struct pad_config early_gpio_table[] = {
 /* SRCCLKREQ2# */	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */
 /* UART0_CTS# */	PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */
+/* SPI_WP_STATUS */	PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP),
 };
 
 #endif



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