[coreboot-gerrit] New patch to review for coreboot: google/lars: Set Correct RCOMP Target for LARs EVT boards

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13005

-gerrit

commit 5763b5f68730a1dfbe41ee2b7cb438ff1e36d1be
Author: Subrata Banik <subrata.banik at intel.com>
Date:   Thu Jan 7 12:17:36 2016 +0530

    google/lars: Set Correct RCOMP Target for LARs EVT boards
    
    Below are correct RCOMP Target Values
    
    Samsung K4E6E304EB part = {100, 40, 40, 21, 40}
    
    Rest all DIMM should have RCOMP as
    {100, 40, 40, 23, 40}
    
    LARs EVT has new DIMM added, earlier RCOMP settings was not
    correct for newly added DIMM cars, causing reboot issue.
    With this patch all DIMM gets its required value programmed.
    
    BRANCH=None
    BUG=None
    TEST=Built for Lars EVT SKU1/2/3 and verified Boot to OS.
    No Reboot after this change.
    
    Change-Id: I5fa5ce47b4b47198b0ae8d0b57f7729cb57d23bf
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: d29cc8a4ad9bc2b7680e4df146ce281738e4a3c4
    Original-Change-Id: I15195b748213553907ff22dbc74651d70f3c7bb6
    Original-Signed-off-by: Subrata Banik <subrata.banik at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/320527
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/lars/pei_data.c | 26 ++++++++++++++++++--------
 1 file changed, 18 insertions(+), 8 deletions(-)

diff --git a/src/mainboard/google/lars/pei_data.c b/src/mainboard/google/lars/pei_data.c
index deb488e..67d8644 100644
--- a/src/mainboard/google/lars/pei_data.c
+++ b/src/mainboard/google/lars/pei_data.c
@@ -22,6 +22,7 @@
 
 /* PCH_MEM_CFG[3:0] */
 #define MAX_MEMORY_CONFIG	0x10
+#define K4E6E304EB_MEM_ID	0x5
 #define RCOMP_TARGET_PARAMS	0x5
 
 void mainboard_fill_pei_data(struct pei_data *pei_data)
@@ -41,19 +42,28 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
 	const u16 RcompResistor[3] = { 200, 81, 162 };
 
 	/* Rcomp target */
-	static const u16 RcompTarget[MAX_MEMORY_CONFIG][RCOMP_TARGET_PARAMS] = {
-		{ 100, 40, 40, 23, 40 },
-		{ 100, 40, 40, 23, 40 },
-		{ 100, 40, 40, 23, 40 },
-		/*Strengthen the Rcomp Target Ctrl for 8GB K4E6E304EE -EGCF*/
-		{ 100, 40, 40, 21, 40 }, };
+	static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = {
+		100, 40, 40, 23, 40
+        };
 
+	/*Strengthen the Rcomp Target Ctrl for 8GB K4E6E304EB -EGCF*/
+	static const u16 StrengthendRcompTarget[RCOMP_TARGET_PARAMS] = {
+		100, 40, 40, 21, 40
+        };
+
+	/* Default Rcomp Target assignment */
+	const u16 *targeted_rcomp = RcompTarget;
 
 	memcpy(pei_data->dq_map, dq_map, sizeof(dq_map));
 	memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map));
 	memcpy(pei_data->RcompResistor, RcompResistor,
 		 sizeof(RcompResistor));
-	memcpy(pei_data->RcompTarget, &RcompTarget[pei_data->mem_cfg_id][0],
-		 sizeof(RcompTarget[pei_data->mem_cfg_id]));
+
+	/* Override Rcomp Target assignment for specific SKU(s) */
+	if (pei_data->mem_cfg_id == K4E6E304EB_MEM_ID)
+		targeted_rcomp = StrengthendRcompTarget;
+
+	memcpy(pei_data->RcompTarget, targeted_rcomp,
+		 sizeof(pei_data->RcompTarget));
 
 }