[coreboot-gerrit] New patch to review for coreboot: intel/skylake: Enable SaGv feature

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12997

-gerrit

commit c60beb1f8a5e0a46013dd1133bf9b811320d818f
Author: haridhar <haridhar.kalvala at intel.com>
Date:   Fri Dec 4 10:41:23 2015 +0530

    intel/skylake: Enable SaGv feature
    
    This change enables SaGv feature for skylake
    platform.As a result of this patch the skylake
    platform will train memory at both low & high
    frequency points.This will be used to
    dynamically scale the work point
    (voltage/frequencies).
    
    The value "3" here means enable. Following
    is the table for same.
    
    0=Disabled(SaGv disabled)
    1=FixedLow(Fixed to low frequency)
    2=FixedHigh(Fixed to High frequency)
    3=Enabled(SaGv Enabled.Dynamically changes)
    
    BRANCH=None
    BUG=chrome-os-partner:48534
    TEST=Built for kunimitsu.
    Tested on D1 silicon.
    
    Change-Id: I2892d631d64495e6aed453af4fd526f4bf5bed68
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 8e09d1a22927f5fcddd6c0be3f9edf3dcb8729be
    Original-Change-Id: I32a7a53805068a52b381affaf061d69062cd8651
    Original-Signed-off-by: haridhar <haridhar.kalvala at intel.com>
    Original-Signed-off-by: Somayaji, Vishwanath <vishwanath.somayaji at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/315806
    Original-Commit-Ready: Haridhar Kalvala <haridhar.kalvala at intel.com>
    Original-Tested-by: Haridhar Kalvala <haridhar.kalvala at intel.com>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-by: Haridhar Kalvala <haridhar.kalvala at intel.com>
---
 src/mainboard/intel/kunimitsu/devicetree.cb | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index f8d2f1e..75bb7c4 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -30,6 +30,7 @@ chip soc/intel/skylake
 	register "SkipExtGfxScan" = "1"
 	register "Device4Enable" = "1"
 	register "HeciEnabled" = "0"
+	register "SaGv" = "3"
 
 	# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
 	# SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s