[coreboot-gerrit] Patch set updated for coreboot: google/lars: Disable SD 3.0 Controller [D30:F6]

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12947

-gerrit

commit 9b44dea75d706ffdacab206a122449b201d20d9a
Author: Subrata Banik <subrata.banik at intel.com>
Date:   Wed Dec 2 12:25:37 2015 +0530

    google/lars: Disable SD 3.0 Controller [D30:F6]
    
    LARs design don't have SD Connector over native SD Controller.
    
    BUG=chrome-os-partner:48190
    BRANCH=None
    TEST=Build & boot LARs. Use "lspci" doesn't list 0x1E:06
    device in list.
    CQ-DEPEND=CL:315420
    
    Change-Id: Idff7243a6aaf4b8d5f49e4bf215a77131f716485
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: ca769138b97b404598c4a6bfa6c2ff5c1c3ec896
    Original-Change-Id: I71416ac89a8c91ab272d6737d1b46c8045567e17
    Original-Signed-off-by: Subrata Banik <subrata.banik at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/315423
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/lars/Kconfig       | 1 +
 src/mainboard/google/lars/devicetree.cb | 4 ++--
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/google/lars/Kconfig b/src/mainboard/google/lars/Kconfig
index 94ec30f..2bf2547 100644
--- a/src/mainboard/google/lars/Kconfig
+++ b/src/mainboard/google/lars/Kconfig
@@ -9,6 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select EC_GOOGLE_CHROMEEC_LPC
 	select EC_GOOGLE_CHROMEEC_MEC
 	select EC_GOOGLE_CHROMEEC_PD
+	select EXCLUDE_NATIVE_SD_INTERFACE
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select HAVE_OPTION_TABLE
diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb
index 677ee0b..d85d25c 100644
--- a/src/mainboard/google/lars/devicetree.cb
+++ b/src/mainboard/google/lars/devicetree.cb
@@ -36,7 +36,7 @@ chip soc/intel/skylake
 	register "Cio2Enable" = "0"
 	register "ScsEmmcEnabled" = "1"
 	register "ScsEmmcHs400Enabled" = "0"
-	register "ScsSdCardEnabled" = "2"
+	register "ScsSdCardEnabled" = "0"
 	register "IshEnable" = "0"
 	register "PttSwitch" = "0"
 	register "InternalGfx" = "1"
@@ -117,7 +117,7 @@ chip soc/intel/skylake
 		device pci 1e.3 off end # GSPI #1
 		device pci 1e.4 on  end # eMMC
 		device pci 1e.5 off end # SDIO
-		device pci 1e.6 on  end # SDCard
+		device pci 1e.6 off  end # SDCard
 		device pci 1f.0 on
 			chip drivers/pc80/tpm
 				device pnp 0c31.0 on end