[coreboot-gerrit] Patch merged into coreboot/master: intel/kunimitsu: Enable 20K PU on LPC_LAD 0-3

gerrit at coreboot.org gerrit at coreboot.org
Fri Jan 15 12:05:21 CET 2016


the following patch was just integrated into master:
commit ff25b7532caa37f6ebb42d9485cbe805c5aec2d1
Author: pchandri <preetham.chandrian at intel.com>
Date:   Mon Nov 30 13:05:53 2015 -0800

    intel/kunimitsu: Enable 20K PU on LPC_LAD 0-3
    
    At S0, S0ix and S3 LPC LAD signals are
    are floated at 400~500mV.
    
    BRANCH=chrome-os-partner:48331
    BUG=None
    TEST=Build and Boot kunimitsu
    
    Change-Id: I2e2654ac89f8e0c8d6ab1af31d0bd5a0d4c43db8
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 6f4b902e220dcde73df56970208c45fe3148b70e
    Original-Change-Id: I597d4816d09d0cfd9b0ec183a9273551aed8688a
    Original-Signed-off-by: pchandri <preetham.chandrian at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/316529
    Original-Commit-Ready: Preetham Chandrian <preetham.chandrian at intel.com>
    Original-Tested-by: Preetham Chandrian <preetham.chandrian at intel.com>
    Original-Tested-by: Kyoung Il Kim <kyoung.il.kim at intel.com>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-by: Preetham Chandrian <preetham.chandrian at intel.com>
    Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati at intel.com>
    Original-Reviewed-by: Kyoung Il Kim <kyoung.il.kim at intel.com>
    Reviewed-on: https://review.coreboot.org/12957
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martinroth at google.com>


See https://review.coreboot.org/12957 for details.

-gerrit



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