[coreboot-gerrit] Patch set updated for coreboot: sb/intel/i82801gx: Fix sata AHCI for desktop NM10/ICH7
Damien Zammit (damien@zamaudio.com)
gerrit at coreboot.org
Fri Jan 15 03:46:46 CET 2016
Damien Zammit (damien at zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12923
-gerrit
commit 056d40beb296b6f8beab2a66a39917a3e39da881
Author: Damien Zammit <damien at zamaudio.com>
Date: Fri Jan 15 13:44:53 2016 +1100
sb/intel/i82801gx: Fix sata AHCI for desktop NM10/ICH7
Tested on Intel D510MO
Before this patch, I was unable to get the SATA controller into AHCI
mode. That is, I could never see PCI ID 8086:27c1 appearing on the bus.
With sata_ahci set, controller now goes into AHCI mode and works. 8086:27c1
Tested on X60 with AHCI enabled 8086:27c5 (AHCI mode for mobile ich7)
No regressions detected.
Change-Id: I4a3eabb5773106a0825fa2f30ee400fbfe636c7f
Signed-off-by: Damien Zammit <damien at zamaudio.com>
---
src/southbridge/intel/i82801gx/i82801gx.c | 6 ++
src/southbridge/intel/i82801gx/sata.c | 109 ++++++++++++++++++++++--------
src/southbridge/intel/i82801gx/sata.h | 10 +++
3 files changed, 98 insertions(+), 27 deletions(-)
diff --git a/src/southbridge/intel/i82801gx/i82801gx.c b/src/southbridge/intel/i82801gx/i82801gx.c
index e344458..6d97088 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.c
+++ b/src/southbridge/intel/i82801gx/i82801gx.c
@@ -18,6 +18,7 @@
#include <device/device.h>
#include <device/pci.h>
#include "i82801gx.h"
+#include "sata.h"
#if !CONFIG_MMCONF_SUPPORT_DEFAULT
#error ICH7 requires CONFIG_MMCONF_SUPPORT_DEFAULT
@@ -31,6 +32,11 @@ void i82801gx_enable(device_t dev)
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_SERR;
pci_write_config32(dev, PCI_COMMAND, reg32);
+
+ if (dev->path.pci.devfn == PCI_DEVFN(31, 2)) {
+ printk(BIOS_DEBUG, "Set SATA mode early\n");
+ sata_enable(dev);
+ }
}
struct chip_operations southbridge_intel_i82801gx_ops = {
diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c
index 29f878d..c78593a 100644
--- a/src/southbridge/intel/i82801gx/sata.c
+++ b/src/southbridge/intel/i82801gx/sata.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2016 Damien Zammit <damien at zamaudio.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -19,14 +20,70 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include "i82801gx.h"
+#include "sata.h"
typedef struct southbridge_intel_i82801gx_config config_t;
+void sata_enable(struct device *dev)
+{
+ /* Get the chip configuration */
+ config_t *config = dev->chip_info;
+
+ /* SATA configuration */
+ pci_write_config32(dev, 0x94,
+ pci_read_config32(dev, 0x94) | (1 << 23) | (1 << 7) | (1 << 8));
+
+ if (config->sata_ahci) {
+ /* Set map to ahci */
+ pci_write_config8(dev, SATA_MAP,
+ (pci_read_config8(dev, SATA_MAP) & ~0xc3) | 0x40);
+
+ /* Set subclass to ahci
+ * (datasheet says RO, but this works) */
+ pci_write_config8(dev, PCI_CLASS_DEVICE, CLASS_AHCI);
+ } else {
+ /* Set map to ide */
+ pci_write_config8(dev, SATA_MAP,
+ pci_read_config8(dev, SATA_MAP) & ~0xc3);
+
+ /* Set subclass to ide
+ * (datasheet says RO, but this works) */
+ pci_write_config8(dev, PCI_CLASS_DEVICE, CLASS_IDE);
+ }
+
+ /* At this point, the new pci id will appear on the bus */
+}
+
+static u8 get_ich7_model(void)
+{
+ struct device *lpc;
+
+ lpc = dev_find_slot(0, PCI_DEVFN(31, 0));
+
+ switch (pci_read_config16(lpc, PCI_DEVICE_ID)) {
+ case 0x27b0:
+ case 0x27b8:
+ return ICH7;
+ case 0x27b9:
+ case 0x27bd:
+ return ICH7M;
+ case 0x27bc:
+ return NM10;
+ default:
+ printk(BIOS_ERR,
+ "i82801gx_sata: error: cannot determine ICH7 model\n");
+ return 0;
+ }
+}
+
static void sata_init(struct device *dev)
{
u32 reg32;
u16 reg16;
+ u8 reg8;
u32 *ahci_bar;
+ u8 ichtype;
+ u8 ports;
/* Get the chip configuration */
config_t *config = dev->chip_info;
@@ -38,7 +95,25 @@ static void sata_init(struct device *dev)
return;
}
- /* SATA configuration */
+ /* Get ICH7 model */
+ ichtype = get_ich7_model();
+
+ /* Enable clock gating for unused ports */
+ switch (ichtype) {
+ default:
+ case ICH7:
+ ports = 0xf;
+ break;
+ case ICH7M:
+ ports = 0x5;
+ break;
+ case NM10:
+ ports = 0x3;
+ break;
+ }
+ reg8 = ((~ports) & 0xf) << 24;
+ pci_write_config32(dev, 0x94,
+ pci_read_config32(dev, 0x94) | reg8);
/* Enable BARs */
pci_write_config16(dev, PCI_COMMAND, 0x0007);
@@ -70,7 +145,7 @@ static void sata_init(struct device *dev)
pci_write_config32(dev, IDE_CONFIG, reg32);
/* Combine IDE - SATA configuration */
- pci_write_config8(dev, 0x90, 0x02);
+ pci_write_config8(dev, SATA_MAP, 0x02);
/* Port 0 & 1 enable */
pci_write_config8(dev, 0x92, 0x0f);
@@ -86,38 +161,18 @@ static void sata_init(struct device *dev)
/* Interrupt Pin is set by D31IP.PIP */
pci_write_config8(dev, INTR_LN, 0x0a);
- /* Set timings */
- pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
- IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
- IDE_PPE0 | IDE_IE0 | IDE_TIME0);
- pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
- IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
-
- /* Sync DMA */
- pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0);
- pci_write_config16(dev, IDE_SDMA_TIM, 0x0001);
-
- /* Set IDE I/O Configuration */
- reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
- pci_write_config32(dev, IDE_CONFIG, reg32);
-
- /* Set Sata Controller Mode. */
- pci_write_config8(dev, 0x90, 0x40); // 40=AHCI
-
/* In ACHI mode, bit[3:0] must always be set
* (Port status is controlled through AHCI BAR)
+ * Different settings for different controller models.
*/
- pci_write_config8(dev, 0x92, 0x0f);
+ pci_write_config8(dev, 0x92, ports);
ahci_bar = (u32 *)(pci_read_config32(dev, 0x27) & ~0x3ff);
ahci_bar[3] = config->sata_ports_implemented;
-
- /* SATA Initialization register */
- pci_write_config32(dev, 0x94, 0x1a000180);
} else {
printk(BIOS_DEBUG, "SATA controller in plain mode.\n");
/* Set Sata Controller Mode. No Mapping(?) */
- pci_write_config8(dev, 0x90, 0x00);
+ pci_write_config8(dev, SATA_MAP, 0x00);
/* No AHCI: clear AHCI base */
pci_write_config32(dev, 0x24, 0x00000000);
@@ -211,11 +266,11 @@ static struct device_operations sata_ops = {
static const unsigned short sata_ids[] = {
0x27c0, /* Desktop Non-AHCI and Non-RAID Mode: 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */
+ 0x27c1, /* Desktop AHCI Mode: 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */
0x27c4, /* Mobile Non-AHCI and Non-RAID Mode: 82801GBM/GHM (ICH7-M/ICH7-M DH) */
+ 0x27c5, /* Mobile AHCI Mode: 82801GBM/GHM (ICH7-M/ICH7-M DH) */
/* NOTE: Any of the below are not properly supported yet. */
- 0x27c1, /* Desktop AHCI Mode: 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */
0x27c3, /* Desktop RAID mode: 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */
- 0x27c5, /* Mobile AHCI Mode: 82801GBM/GHM (ICH7-M/ICH7-M DH) */
0x27c6, /* ICH7M DH Raid Mode: 82801GHM (ICH7-M DH) */
0
};
diff --git a/src/southbridge/intel/i82801gx/sata.h b/src/southbridge/intel/i82801gx/sata.h
new file mode 100644
index 0000000..e06512c
--- /dev/null
+++ b/src/southbridge/intel/i82801gx/sata.h
@@ -0,0 +1,10 @@
+#define ICH7 0x1
+#define ICH7M 0x2
+#define NM10 0x4
+
+#define CLASS_AHCI 0x6
+#define CLASS_IDE 0x1
+
+#define SATA_MAP 0x90
+
+void sata_enable(struct device *dev);
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