[coreboot-gerrit] New patch to review for coreboot: intel/kunimitsu: Correct the output for crossystem wpsw_boot

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12952

-gerrit

commit e24491b929594022cd1b0e042b88f31f3ae850db
Author: Arindam Roy <arindam.roy at intel.com>
Date:   Fri Dec 4 16:46:24 2015 -0800

    intel/kunimitsu: Correct the output for crossystem wpsw_boot
    
    The write protect GPIO is not being configured early enough.
    This is leading to coreboot reading incorrect value, and
    writing the incorrect value in vboot shared file.
    This is leading to "crossystem wpsw_boot" always returning 0
    even with the write protect screw in place during boot.
    
    BUG=chrome-os-partner:48292
    BRANCH=None
    TEST=Boot with the write protect screw in place. Issue
    crossystem wpsw_boot. It should show 1.
    
    Change-Id: I3a333a4dcce31be9afe28cf11b127090cc7b9421
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 462dd0229c2d3b81cd34bdd2e36bea844f58586c
    Original-Change-Id: Ib7e0539845575b32322e243e89b81ffee077eb81
    Original-Signed-off-by: Arindam Roy <arindam.roy at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/316009
    Original-Commit-Ready: Arindam Roy <rarindam at gmail.com>
    Original-Tested-by: Arindam Roy <rarindam at gmail.com>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/intel/kunimitsu/gpio.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/intel/kunimitsu/gpio.h b/src/mainboard/intel/kunimitsu/gpio.h
index cfec92e..f027326 100755
--- a/src/mainboard/intel/kunimitsu/gpio.h
+++ b/src/mainboard/intel/kunimitsu/gpio.h
@@ -231,6 +231,7 @@ static const struct pad_config gpio_table[] = {
 static const struct pad_config early_gpio_table[] = {
 /* SRCCLKREQ2# */	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */
 /* UART0_CTS# */	PAD_CFG_GPO(GPP_C11, 1, DEEP), /* EN_PP3300_KEPLER */
+/* SPI_WP_STATUS */	PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP),
 };
 
 #endif