[coreboot-gerrit] New patch to review for coreboot: google/lars: Disable kepler device

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12950

-gerrit

commit f392b6d6f13d9992c352feedd31a360699bc5be7
Author: david <david_wu at quantatw.com>
Date:   Fri Dec 4 14:04:15 2015 +0800

    google/lars: Disable kepler device
    
    Disable kepler device, it is removed and was not used on proto anyway.
    
    BUG=none
    BRANCH=none
    TEST=build and boot on lars proto
    
    Change-Id: I137b82b8dca23f5b40adcc6a056e77a4ff54d4d5
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 44d63453a9b31331d13d05f8f86d4218af0f0aa1
    Original-Change-Id: Ib0892bf93b1d0cda1c0143d2b16cd58aeda83131
    Original-Signed-off-by: David Wu <David_Wu at quantatw.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/315950
    Original-Commit-Ready: David Wu <david_wu at quantatw.com>
    Original-Tested-by: David Wu <david_wu at quantatw.com>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-by: Subrata Banik <subrata.banik at intel.com>
---
 src/mainboard/google/lars/devicetree.cb | 9 +++------
 src/mainboard/google/lars/gpio.h        | 4 ++--
 2 files changed, 5 insertions(+), 8 deletions(-)

diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb
index 454f01d..d85d25c 100644
--- a/src/mainboard/google/lars/devicetree.cb
+++ b/src/mainboard/google/lars/devicetree.cb
@@ -43,15 +43,12 @@ chip soc/intel/skylake
 	register "SkipExtGfxScan" = "1"
 	register "Device4Enable" = "1"
 
-	# Enable Root port 1 and 5.
+	# Enable Root port 1.
 	register "PcieRpEnable[0]" = "1"
-	register "PcieRpEnable[4]" = "1"
 	# Enable CLKREQ#
 	register "PcieRpClkReqSupport[0]" = "1"
-	register "PcieRpClkReqSupport[4]" = "1"
-	# RP 1 uses SRCCLKREQ1# while RP 5 uses SRCCLKREQ2#
+	# RP 1 uses SRCCLKREQ1#
 	register "PcieRpClkReqNumber[0]" = "1"
-	register "PcieRpClkReqNumber[4]" = "2"
 
 	register "usb2_ports[0]" = "USB2_PORT_TYPE_C"  # Type-C Port 1
 	register "usb2_ports[1]" = "USB2_PORT_FLEX"    # Camera
@@ -106,7 +103,7 @@ chip soc/intel/skylake
 		device pci 1c.1 off end # PCI Express Port 2
 		device pci 1c.2 off end # PCI Express Port 3
 		device pci 1c.3 off end # PCI Express Port 4
-		device pci 1c.4 on  end # PCI Express Port 5
+		device pci 1c.4 off end # PCI Express Port 5
 		device pci 1c.5 off end # PCI Express Port 6
 		device pci 1c.6 off end # PCI Express Port 7
 		device pci 1c.7 off end # PCI Express Port 8
diff --git a/src/mainboard/google/lars/gpio.h b/src/mainboard/google/lars/gpio.h
index 7ebeb5d..0c2ef32 100755
--- a/src/mainboard/google/lars/gpio.h
+++ b/src/mainboard/google/lars/gpio.h
@@ -112,7 +112,7 @@ static const struct pad_config gpio_table[] = {
 /* UART0_RXD */		/* GPP_C8 */
 /* UART0_TXD */		/* GPP_C9 */
 /* NFC_RST* */		PAD_CFG_GPO(GPP_C10, 0, DEEP),
-/* EN_PP3300_KEPLER */	PAD_CFG_TERM_GPO(GPP_C11, 1, 20K_PD, DEEP),
+/* EN_PP3300_KEPLER */	PAD_CFG_TERM_GPO(GPP_C11, 0, 20K_PD, DEEP),
 /* PCH_MEM_CFG0 */	PAD_CFG_GPI(GPP_C12, NONE, DEEP),
 /* PCH_MEM_CFG1 */	PAD_CFG_GPI(GPP_C13, NONE, DEEP),
 /* PCH_MEM_CFG2 */	PAD_CFG_GPI(GPP_C14, NONE, DEEP),
@@ -222,7 +222,7 @@ static const struct pad_config gpio_table[] = {
 /* Early pad configuration in romstage. */
 static const struct pad_config early_gpio_table[] = {
 /* SRCCLKREQ2# */	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */
-/* UART0_CTS# */	PAD_CFG_GPO(GPP_C11, 1, DEEP), /* EN_PP3300_KEPLER */
+/* UART0_CTS# */	PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */
 };
 
 #endif