[coreboot-gerrit] New patch to review for coreboot: intel/skylake: Enable SkipMpInit token

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12943

-gerrit

commit 206694355c02fd8612296b6aafe77a5e3f0bd3e8
Author: Rizwan Qureshi <rizwan.qureshi at intel.com>
Date:   Thu Nov 19 16:27:03 2015 +0530

    intel/skylake: Enable SkipMpInit token
    
    This patch helps to enable SkipMpInit token of FSP SiliconInit UPD
    
    BRANCH=none
    BUG=chrome-os-partner:44805
    TEST=Build and booted in kunimitsu with SkipMpInit enabled from CB.
    
    CQ-DEPEND=CL:310869
    
    Change-Id: I43377e4b8adadf42091a9387883363fdfbab4c1b
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: b7962273fd1a591cfe9a658f49ebc7d23bcad577
    Original-Change-Id: I977d2d39c283d74f1aa9033c8aa60dc652735019
    Original-Signed-off-by: Barnali Sarkar <barnali.sarkar at intel.com>
    Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi at intel.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/310192
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/skylake/chip.c | 2 ++
 src/soc/intel/skylake/chip.h | 1 +
 2 files changed, 3 insertions(+)

diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 951e461..a6df0f3 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -345,6 +345,8 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
 	params->SerialIrqConfigSirqMode = config->SerialIrqConfigSirqMode;
 	params->SerialIrqConfigStartFramePulse = config->SerialIrqConfigStartFramePulse;
 
+	params->SkipMpInit = config ->SkipMpInit;
+
 	/* Show SPI controller if enabled in devicetree.cb */
 	dev = dev_find_slot(0, PCH_DEVFN_SPI);
 	params->ShowSpiController = dev->enabled;
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 94a2b73..2a1980c 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -324,6 +324,7 @@ struct soc_intel_skylake_config {
 	 * Values: 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2; PchSfpw8Clk.
 	 */
 	u8 SerialIrqConfigStartFramePulse;
+	u8 SkipMpInit;
 };
 
 typedef struct soc_intel_skylake_config config_t;