[coreboot-gerrit] Patch set updated for coreboot: Braswell: Fix P-state table

[Hannah Williams (hannah.williams@intel.com)]

Hannah Williams (hannah.williams at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12731

-gerrit

commit f878ae165fe3640b4e940dfa1372e47f5fb2f828
Author: Subrata Banik <subrata.banik at intel.com>
Date:   Wed Aug 5 17:01:55 2015 +0530

    Braswell: Fix P-state table
    
    Incorrect bus-core-ratio been used to generate P-state table
    
    Original-Reviewed-on: https://chromium-review.googlesource.com/290681
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    
    Change-Id: I4a34ec80ff3f2ed46dc074c9f8fe06756db8b357
    Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
 src/soc/intel/braswell/include/soc/msr.h    |  3 ++-
 src/soc/intel/braswell/include/soc/pattrs.h |  2 +-
 src/soc/intel/braswell/ramstage.c           |  2 +-
 src/soc/intel/braswell/tsc_freq.c           | 32 ++++++++++++++++++++++++++---
 4 files changed, 33 insertions(+), 6 deletions(-)

diff --git a/src/soc/intel/braswell/include/soc/msr.h b/src/soc/intel/braswell/include/soc/msr.h
index 93701aa..d998e68 100644
--- a/src/soc/intel/braswell/include/soc/msr.h
+++ b/src/soc/intel/braswell/include/soc/msr.h
@@ -43,6 +43,7 @@
 #define MSR_CPU_THERM_CFG2		0x674
 #define MSR_CPU_THERM_SENS_CFG		0x675
 
-#define BUS_FREQ_KHZ			100000	/* 100 MHz */
+/* Read BCLK from MSR */
+unsigned int cpu_bus_freq_khz(void);
 
 #endif /* _SOC_MSR_H_ */
diff --git a/src/soc/intel/braswell/include/soc/pattrs.h b/src/soc/intel/braswell/include/soc/pattrs.h
index 439d0bd..d86f9ee 100644
--- a/src/soc/intel/braswell/include/soc/pattrs.h
+++ b/src/soc/intel/braswell/include/soc/pattrs.h
@@ -44,7 +44,7 @@ struct pattrs {
 	const void *microcode_patch;
 	int address_bits;
 	int num_cpus;
-	unsigned bclk_khz;
+	unsigned int bclk_khz;
 };
 
 /*
diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c
index 749feaf..1e085d7 100644
--- a/src/soc/intel/braswell/ramstage.c
+++ b/src/soc/intel/braswell/ramstage.c
@@ -128,7 +128,7 @@ static void fill_in_pattrs(void)
 	attrs->iacore_vids[IACORE_TURBO] = (msr.lo & 0xff); /* 1 core max */
 
 	/* Set bus clock speed */
-	attrs->bclk_khz = BUS_FREQ_KHZ;
+	attrs->bclk_khz = cpu_bus_freq_khz();
 }
 
 static inline void set_acpi_sleep_type(int val)
diff --git a/src/soc/intel/braswell/tsc_freq.c b/src/soc/intel/braswell/tsc_freq.c
index 284ba2b..fff882e 100644
--- a/src/soc/intel/braswell/tsc_freq.c
+++ b/src/soc/intel/braswell/tsc_freq.c
@@ -26,12 +26,38 @@
 #endif
 #include <stdint.h>
 
+static const unsigned int cpu_bus_clk_freq_table[] = {
+	83333,
+	100000,
+	133333,
+	116666,
+	80000,
+	93333,
+	90000,
+	88900,
+	87500
+};
+
+unsigned int cpu_bus_freq_khz(void)
+{
+	msr_t clk_info = rdmsr(MSR_BSEL_CR_OVERCLOCK_CONTROL);
+	if((clk_info.lo & 0xF)  < (sizeof(cpu_bus_clk_freq_table)/sizeof(unsigned int)))
+	{
+		return(cpu_bus_clk_freq_table[clk_info.lo & 0xF]);
+	}
+	return 0;
+}
+
 unsigned long tsc_freq_mhz(void)
 {
-	msr_t ia_core_ratios;
+	msr_t platform_info;
+	unsigned int bclk_khz = cpu_bus_freq_khz();
+
+	if (!bclk_khz)
+		return 0;
 
-	ia_core_ratios = rdmsr(MSR_IACORE_RATIOS);
-	return (BUS_FREQ_KHZ * ((ia_core_ratios.lo >> 16) & 0x3f)) / 1000;
+	platform_info = rdmsr(MSR_PLATFORM_INFO);
+	return (bclk_khz * ((platform_info.lo >> 8) & 0xff)) / 1000;
 }
 
 #if !ENV_SMM