[coreboot-gerrit] Patch set updated for coreboot: google/lars: Disable eMMC HS400 capability

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12618

-gerrit

commit 48cd5239f8641984569211ff838c6d0999a43c54
Author: david <david_wu at quantatw.com>
Date:   Tue Nov 24 14:41:35 2015 +0800

    google/lars: Disable eMMC HS400 capability
    
    BUG=chrome-os-partner:48017
    BRANCH=none
    TEST=Verify eMMC is working fine.
    
    Change-Id: If02d969029a9eb8d05148ee958fd34225c8a88fe
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: dca385c2bbf11c9eb79fd0761b2b335f8fdff491
    Original-Change-Id: I371036426f17530409b46af285b18f4522739ee7
    Original-Signed-off-by: David Wu <David_Wu at quantatw.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/313912
    Original-Commit-Ready: David Wu <david_wu at quantatw.com>
    Original-Tested-by: David Wu <david_wu at quantatw.com>
    Original-Reviewed-by: David Wu <david_wu at quantatw.com>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-by: Subrata Banik <subrata.banik at intel.com>
---
 src/mainboard/google/lars/devicetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb
index cb49968..d743921 100644
--- a/src/mainboard/google/lars/devicetree.cb
+++ b/src/mainboard/google/lars/devicetree.cb
@@ -35,7 +35,7 @@ chip soc/intel/skylake
 	register "SmbusEnable" = "1"
 	register "Cio2Enable" = "0"
 	register "ScsEmmcEnabled" = "1"
-	register "ScsEmmcHs400Enabled" = "1"
+	register "ScsEmmcHs400Enabled" = "0"
 	register "ScsSdCardEnabled" = "2"
 	register "IshEnable" = "0"
 	register "PttSwitch" = "0"